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參數(shù)資料
| 型號(hào)： | D6571E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Chip for an All-Digital Telephone Answering Machine with Flash Memory Interface |
| 中文描述： | 芯片的全數(shù)字電話應(yīng)答機(jī)與快閃記憶體介面 |
| 文件頁(yè)數(shù)： | 86/117頁(yè) |
| 文件大小： | 551K |
| 代理商： | D6571E |
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D6571E Data Sheet
DS6571E.2
DSP GROUP, INC., 3120 SCOTT BOULEVARD
SANTA CLARA, CA 95054 PH: 408 986-4300 FAX: 408 986-4490
84
FUNCTIONAL BLOCKS
The block diagram in Figure 5 shows the D6571E functional blocks and interface functional blocks and interface.
CODEC
DATA/CONTROL
XTAL
DSP DATA BUS
CLOCK
GENERATOR
CODEC
INTERFACE
I/O ADDRESS
DECODER
FLASH
INTERFACE
INTERFACE
HOST
COMMUNICATION
CONTROL BUS
MEMORY ADDRESS
BUS
FLASH
READ/WRITE
FLRD/FLWR
Figure 5. D6571E-11 Block Diagram
FLASH
DATA
HOST
CONTROL
HOST
DATA BUS
ADDRESS MUX
DSP
CLOCK
uLAW
ENCODER
D0091A
DSP I/O
SELECT
DSP
CORE
DSP CORE
At the heart of the chipset is the DSP core. All of the
software algorithms such as compression, decompression,
tone detection, tone generation, and echo cancellation run
on that processor. The DSP core controls the system,
memory and message management. The DSP program
ROM is masked internally. The DSP is connected via an
internal bus to most of the other modules within the
D6571E-11 chip.
ADDRESS MUX
Address MUX controls external memory select signals
and memory address bus.
FLASH MEMORY INTERFACE
The Flash memory interface provides access to the Flash
memory message storage. The interface supports up to 4
Flash devices with 4 Mbit configuration and 1 device with
16 Mbit configuration.
CLOCK GENERATOR
This block provides clock signals to the DSP core and all
the internal devices. It also includes clock rate reduction
in Power Down mode.
m
-law/A-law ENCODER
This interface provides converting linear code (14-bit) to
8-bit
μ
-law or A-law PCM code.
CODEC INTERFACE
The CODEC Interface implements the data transfer and
synchronization functions required interfacing the DSP
with the CODEC chip. The data transfer to/from the
CODECs is serial. The CODEC interface supports fixed
and variable rate CODECs.
I/O ADDRESS DECODER
The I/O Address Decoder generates the required I/O read
and write pulses for the internal DSP peripheral devices.
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