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參數(shù)資料
| 型號(hào)： | D2-24044-MR-T |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 6/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL AMP AUDIO PWR D 38HTSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | D2Audio™ |
| 類型： | D 類 |
| 輸出類型： | 2-通道（立體聲）或 4 通道（四路） |
| 在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量： | 30W x 2 @ 8 歐姆 |
| 電源電壓： | 9 V ~ 26 V |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 38-HTSSOP |
| 封裝/外殼： | 38-TFSOP （0.173"，4.40mm 寬）裸露焊盤 |
| 包裝： | 帶卷 (TR) |
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14
FN7678.0
September 3, 2010
Output Mode Configurations
The D2-24044 device supports four amplifier output
configuration modes, utilizing the device’s 4 power stage
outputs.
Configuration selection is controlled by the OCFG0 and
OCFG1 pins, by connecting them to either a high
(+3.3V, PWMVDD = 1) or low (ground = 0) level.
Settings are chosen based on the output configuration
and topology of the design. Their connection is to be
hard-connected on the design, and they are not
intended to be dynamic or subject to change during
system operation.
For each of the four configurations, the PWM input pin
signals route to the individual FETs of each of the power
stages to implement the channel drive and topology
needed for those configurations. Figures 11, 12, 13, and
14 show this routing of the PWM inputs to each of the
power stages, and how the particular topology is
implemented for that configuration. Table 1 shows the
configuration functions that are defined with the
combinations of the OCFG pins, and these diagrams
show the implementation that is listed in this table.
TABLE 1. D2-24044 CONFIGURATION PWM AND OUTPUT CHANNEL ASSIGNMENTS
CONFIG PINS
CONFIG
CONFIGURATION
DESCRIPTION
POWER STAGE OUTPUT
nERROR CHANNEL USE
OCFG1 OCFG0
OUTA
OUTB
OUTC
OUTD
nERRORA nERRORB nERRORC nERRORD
0
“00”
2-Channel
Full Bridge
3-Level
PWM Drive
(Ref. Figure 11)
Output
Channel 1
Output
Channel 2
Connect (wire-or)
nERRORA & nERRORB
together.
Use for Output
Channel 1 Protect
Connect (wire-or)
nERRORC & nERRORD
together.
Use for Output
Channel 2 Protect
High-Side FET PWM Input Assignments
PWM1
PWM3
PWM5
PWM7
Low-Side FET PWM Input Assignments
PWM2
PWM4
PWM6
PWM8
0
1
“01”
2-Channel
Full Bridge,
2-Quadrant PWM Drive
(Ref. Figure 12)
Output
Channel 1
Output
Channel 2
Connect (wire-or)
nERRORA & nERRORB
together.
Use for Output
Channel 1 Protect
Connect (wire-or)
nERRORC & nERRORD
together.
Use for Output
Channel 2 Protect
High-Side FET PWM Input Assignments
PWM1
PWM2
PWM3
PWM4
Low-Side FET PWM Input Assignments
PWM2
PWM1
PWM4
PWM3
1
0
“10”
2-Channel
Half-Bridge
plus
1-Channel
Full Bridge
(Ref. Figure 13)
Output
Ch. 1
Output
Ch 2
Output
Channel 3
nERRORA
Use for
Channel 1
Protect
nERRORB
Use for
Channel 2
Protect
Connect (wire-or)
nERRORC & nERRORD
together.
Use for Output
Channel 3 Protect
High-Side FET PWM Input Assignments
PWM1
PWM3
PWM5
PWM6
Low-Side FET PWM Input Assignments
PWM2
PWM4
PWM6
PWM5
1
“11”
4-Channel
Half-Bridge
(Ref. Figure 14)
Output
Ch. 1
Output
Ch 2
Output
Ch. 3
Output
Ch 4
nERRORA
Use for
Channel 1
Protect
nERRORB
Use for
Channel 2
Protect
nERRORC
Use for
Channel 3
Protect
nERRORD
Use for
Channel 4
Protect
High-Side FET PWM Input Assignments
PWM1
PWM3
PWM5
PWM7
Low-Side FET PWM Input Assignments
PWM2
PWM4
PWM6
PWM8
D2-24044
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