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參數(shù)資料
| 型號(hào)： | CYNSE70256 |
| 英文描述： | Network Processing |
| 中文描述： | 網(wǎng)絡(luò)處理 |
| 文件頁(yè)數(shù)： | 18/126頁(yè) |
| 文件大?。?/td> | 3302K |
| 代理商： | CYNSE70256 |
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CYNSE70032
Document #: 38-02042 Rev. *E
Page 18 of 126
11.0
Data and Mask Addressing
Figure 11-1
shows CYNSE70032 data and mask array addressing.
68
12.0
Commands
A master device such as an ASIC controller issues commands to the CYNSE70032 device using the command valid (CMDV)
signal and the CMD bus. The following subsections describe the operation of the commands.
12.1
The CYNSE70032 device implements four basic commands, shown in
Table 12-1
. The command code must be presented to
CMD[1:0] while keeping the CMDV signal high for two CLK2X cycles (cycles A and B). The controller ASIC must align the
instructions using the PHS_L signal. The CMD[8:2] field passes the parameters of the command in cycles A and B.
Command Codes
Table 12-1. Command Codes
Command Code
00
01
10
Command
Read
Write
Search
Description
Reads one of the following: data array, mask array, device registers, or external SRAM.
Writes one of the following: data array, mask array, device registers, or external SRAM.
Searches the data array for a desired pattern using the specified register from the GMR
array and local mask associated with each data cell.
The device has internal storage for up to 16 comparands that it can learn. The device
controller can insert these entries at the next free address (as specified by the NFA
register) using the Learn instruction.
11
Learn
2 K
136
4 K
68
4 K
68
1 K
272
Figure 10-2. Multiwidth Database Configurations
CFG = 10010000
CFG = 00000000
(68-bit configuration)
CFG = 10101010
(272-bit configuration)
67
0
0
1
2
3
16383
283
0
68
68
3
7
2
6
1
5
0
4
16380
16381
16382
16383
68
68
CFG = 01010101
(136-bit configuration)
135
0
68
68
1
3
5
7
0
2
4
6
16382
16383
16K
4K
64K
Figure 11-1. Addressing CYNSE70032 Data and Mask Arrays
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