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參數(shù)資料
| 型號： | CYNSE70256 |
| 英文描述： | Network Processing |
| 中文描述： | 網(wǎng)絡(luò)處理 |
| 文件頁數(shù)： | 15/126頁 |
| 文件大?。?/td> | 3302K |
| 代理商： | CYNSE70256 |
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CYNSE70032
Document #: 38-02042 Rev. *E
Page 15 of 126
9.0
Information Register
Table 9-1
describes the information register fields.
TLSZ
[3:2]
01
Table Size
. The host ASIC must program this field to configure the chips into a table of
a certain size. This field affects the pipeline latency of the Search and Learn operations
as well as the Read and Write accesses to the SRAM (SADR[21:0], CE_L, OE_L, WE_L,
ALE_L, SSV, SSF, and ACK). Once programmed, the Search latency stays constant.
The latency by number of CLK cycles is as follows:
00: One device
4
01: Up to eight devices 5
10: Up to 31 devices
6
11: Reserved.
Latency of Hit Signals
.
This field further adds latency to the SSF and SSV signals by
the following number of CLK cycles during searches and ACKs in an SRAM Read access:
000: 0
100: 4
001: 1
101: 5
010: 2
110: 6
011: 3
111: 7.
Last Device in the Cascade
. When set, this is the last device in the depth-cascaded
table and is the default driver for the SSF and SSV signals. In the event of a Search failure,
the device with this bit set drives the hit signals as follows: SSF = 0, SSV = 1.
During nonSearch cycles, the device with this bit set drives the signals as follows:
SSF = 0, SSV = 0.
Last Device on the SRAM Bus
. When set, this device is the last device on the SRAM
bus in the depth-cascaded table and is the default driver for the SADR, CE_L, WE_L, and
ALE_L signals. In cycles where no CYNSE70032 device (in a depth-cascaded table)
drives these signals, the signals are driven as follows: SADR = 22’h3FFFFF, CE_L = 1,
WE_L = 1, and ALE_L = 1. OE_L is always driven by the device for which this bit is set.
Database Configuration
. The device is divided internally into four partitions of 8K × 68
bits, each of which can be configured as 8K × 68 bits, 4K × 136 bits, or 2K × 272 bits, as
follows:
00: 4K × 68 bits
01: 2K × 136 bits
10: 1K × 272 bits
11: Reserved.
Bits[10:9] apply to configuring the first
partition in the address space.
Bits[12:11] apply to configuring the second partition in the address space.
Bits[14:13] apply to configuring the third partition in the address space.
Bits[16:15] apply to configuring the fourth partition in the address space.
Reserved
.
HLAT
[6:4]
000
LDEV
[7]
0
LRAM
[8]
0
CFG
[16:9]
00000000
[67:17]
0
Table 9-1. Information Register Description
Field
Revision
Range
[3:0]
Initial Value
0001
Description
Revision Number
. This is the current device revision number. Numbers
start at one and increment by one for each revision of the device.
This is the device implementation number.
Reserved
.
This is the device identification number.
Reserved
.
These are the three most significant bits of the device identification
number.
Manufacturer ID
. This field is the same as the manufacturer identifi-
cation number and continuation bits in the TAP controller.
Reserved
.
Implementation
Reserved
Device ID
Device ID
Device ID
[6:4]
[7]
[11:8]
[12]
[15:13]
000
0
0001
0 or 1
000
MFID
[31:16]
1101_1100_0111_1111
Reserved
[67:32]
Table 8-1. Command Register Description
(continued)
Field
Range
Initial Value
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CZET101 | Clock Driver |
| CZEU101 | Quad Peripheral Driver |
| CZEZ101 | Triple Peripheral Driver |
| CZSP103 | Voltage Reference |
| CZT122 | TRANSISTOR | BJT | DARLINGTON | NPN | 100V V(BR)CEO | 5A I(C) | SOT-223 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYNSE70256-66BGC | 制造商:Cypress Semiconductor 功能描述: |
| CYNSE70256-66BHC | 制造商:Cypress Semiconductor 功能描述:COMMUNICATIONS, NETWORK SEARCH ENGINE - Trays |
| CYONS10017-LBXC | 制造商:Cypress Semiconductor 功能描述: |
| CYONS1001G-LBXC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| CYONS1001L | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:OvationONS⑩ 1L - Laser Navigation Sensor |
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