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| 型號(hào)： | CYNSE70128 |
| 英文描述： | Network Processing |
| 中文描述： | 網(wǎng)絡(luò)處理 |
| 文件頁(yè)數(shù)： | 68/126頁(yè) |
| 文件大小： | 3302K |
| 代理商： | CYNSE70128 |
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CYNSE70032
Document #: 38-02042 Rev. *E
Page 68 of 126
entry and the hit flag (see page 14 for the description of SSR[0:7]). The DQ[67:0] is driven with 68-bit data ([67:0])to be compared
against all odd locations.
A logical 136-bit Search operation is shown in
Figure 13-44
. The entire table made up of 31 devices and consisting of 136-bit
entries is compared against a 136-bit word K that is presented on the DQ bus (using the GMR and local mask bits) in cycles A
and B of the command. The GMR is the 136-bit word specified by the even and odd global mask pair selected by the GMR Index
in the command’s cycle A.
The 136-bit word K that is presented on the DQ bus in cycles A and B of the command is also stored in the even and odd
comparand registers specified by the Comparand Register Index in the command’s cycle B. In ×136 configurations, the even and
odd comparand registers can subsequently be used by the Learn command in the first non-full device only.
Note
. The Learn
command is supported for only one of the blocks consisting of up to eight devices in a depth-cascaded table of more than one
block. The word K that is presented on the DQ bus in cycles A and B of the command is compared with each entry in the table,
starting at location 0. The first matching entry’s location address L is the winning address that is driven as part of the SRAM
address on the SADR[21:0] lines (see Section 15.0, “SRAM Addressing” on page 98). The global winning device will drive the
bus in a specific cycle. In global miss cycles, the device with LRAM = 1 (the default driving device for the SRAM bus) and LDEV
= 1 (the default driving device for SSF and SSV signals) will be the default driver for such missed cycles.
Note
. During 136-bit
searches of 136-bit-configured tables, the Search hit will always be at an even address.
135
Must be same in each of the 31
devices
The Search command is a pipelined operation. It executes a Search at half the rate of the frequency of CLK2X for 136-bit searches
in ×136-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 136-bit Search command cycle
(two CLK2X cycles) is shown in
Table 13-15
.
Search latency from command to SRAM access cycle is 6 for 1–31 devices in the table and TLSZ = 10. In addition, SSV and
SSF shift further to the right for different values of HLAT, as specified in
Table 13-16
.
Table 13-15. Search Latency from Instruction to SRAM Access Cycle
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Max Table Size
8K × 136 bits
64K × 136 bits
248K × 136 bits
Latency in CLK Cycles
4
5
6
Table 13-16. Shift of SSF and SSV from SADR
HLAT
000
001
010
011
100
101
110
111
Number of CLK Cycles
0
1
2
3
4
5
6
7
CFG = 01010101
(136-bit configuration)
135
0
Location
address
0
2
4
6
507902
K
GMR
Comparand Register (odd)
B
Comparand Register (even)
A
0
67
0
(First matching entry)
L
A
B
Even
Odd
Will be same in each of the 31
devices
Figure 13-44. x136 Table with 31 Devices
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