參數(shù)資料
型號(hào)： CYNSE70128
英文描述： Network Processing
中文描述： 網(wǎng)絡(luò)處理
文件頁數(shù)： 23/126頁
文件大?。?/td> 3302K
代理商： CYNSE70128
CYNSE70032
Document #: 38-02042 Rev. *E
Page 23 of 126
The burst Write operation lasts for (n + 2) CLK cycles. n signifies the number of accesses in the burst as specified in the BLEN
field of the WBURREG. The following is the block Write operation sequence. This operation assumes that the host ASIC has
programmed the WBURREG with the ADR and the BLEN before initiating a burst Write command.
Cycle 1A
: The host ASIC applies the Write instruction to CMD[1:0] (CMD[2] = 1) using CMDV = 1, and the address supplied
on the DQ bus, as shown in
Table 12-9
. The host ASIC also supplies the GMR Index to mask the Write to the data or mask
array locations in CMD[5:3].
Cycle 1B
: The host ASIC continues to apply the Write instruction on CMD[1:0] (CMD[2] = 1) using CMDV = 1 and the address
supplied on the DQ bus. The host ASIC continues to supply the GMR Index to mask the Write to the data or mask array
locations in CMD[5:3]. The host ASIC selects the device for which ID[4:0] matches the DQ[25:21] lines. It selects all the devices
when DQ[25:21] = 11111.
Cycle 2
: The host ASIC drives the DQ[67:0] with the data to be written to the data or mask array location of the selected device.
The CYNSE70032 device writes the data from the DQ[67:0] bus only to the subfield that has the corresponding mask bit set
to 1 in the GMR specified by the index CMD[5:3]supplied in cycle 1.
Cycles 3 to n + 1
: The host ASIC drives DQ[67:0] with the data to be written to the next data or mask array location of the
selected device (addressed by the auto-increment ADR field of the WBURREG register).
The CYNSE70032 device writes the data on the DQ[67:0] bus only to the subfield that has the corresponding mask bit set to 1
in the GMR that is specified by the index CMD[5:3] supplied in cycle 1. The CYNSE70032 device drives the EOT signal low from
cycle 3 to cycle n; the CYNSE70032 device drives the EOT signal high in cycle n + 1 (n is specified in the BLEN field of the
WBURREG).
Cycle n + 2
: TheCYNSE70032 drives the EOT signal low.
At the termination of cycle n + 2, the CYNSE70032 device floats the EOT signal to a three-state operation, and a new instruction
can begin.
Table 12-9. Write Address Format for Data and Mask Array (Burst Write)
DQ
[67:26]
[25:21]
[20:19]
Reserved
ID
00: Data array
DQ
DQ
DQ
[18:14]
Reserved
DQ[13:0]
Do not care
. These fifteen bits come from the internal
WBURADR, which increments with each access.
Do not care
. These fifteen bits come from the internal
WBURADR, which increments with each access.
Reserved
ID
01: Mask array
Reserved
1
Data0
Data1 Data2
X
Data3
Write
Address
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
CMD[1:0]
DQ
CLK2X
EOT
CMD[8:2]
A
B
PHS_L
CMDV
Figure 12-4. Burst Write of the Data and Mask Arrays (BLEN = 4)
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