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參數(shù)資料
| 型號： | CY7B991V-5JCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Low Voltage Programmable Skew Clock Buffer |
| 中文描述： | 7B SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大小： | 293K |
| 代理商： | CY7B991V-5JCT |
CY7B991V
3.3V RoboClock
Document Number: 38-07141 Rev. *C
Page 5 of 14
Operational Mode Descriptions
Figure 2
shows the LVPSCB configured as a zero skew clock buffer. In this mode, the CY7B991V is the basis for a low skew clock
distribution tree. When all of the function select inputs (xF0, xF1) are left open, the outputs are aligned and drive a terminated
transmission line to an independent load. The FB input is tied to any output in this configuration and the operating frequency range
is selected with the FS pin. The low skew specification, coupled with the ability to drive terminated transmission lines (with impedances
as low as 50 ohms), enables efficient printed circuit board design.
Figure 3
shows a configuration to equalize skew between metal traces of different lengths. In addition to low skew between outputs,
the LVPSCB is programmed to stagger the timing of its outputs. The four groups of output pairs are each programmed to different
output timing. Skew timing is adjusted over a wide range in small increments with the appropriate strapping of the function select pins.
In this configuration, the 4Q0 output is sent back to FB and configured for zero skew. The other three pairs of outputs are programmed
to yield different skews relative to the feedback. By advancing the clock signal on the longer traces or retarding the clock signal on
shorter traces, all loads receive the clock pulse at the same time.
Figure 2. Zero Skew and Zero Delay Clock Driver
Figure 3. Programmable Skew Clock Driver
SYSTEM
CLOCK
L1
L2
L3
L4
LENGTH L1 = L2 = L3 = L4
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
Z
0
LOAD
LOAD
LOAD
LOAD
REF
Z
0
Z
0
Z
0
LENGTH L1 = L2
L3 < L2 by 6 inches
L4 > L2 by 6 inches
SYS-
TEM
CLOCK
L1
L2
L3
L4
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
Z
0
LOAD
LOAD
LOAD
LOAD
REF
Z
0
Z
0
Z
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7B991V-5JIT | Low Voltage Programmable Skew Clock Buffer |
| CY7B991V-5JXC | Low Voltage Programmable Skew Clock Buffer |
| CY7B991V-5JXCT | Low Voltage Programmable Skew Clock Buffer |
| CY7B991V-5JXI | Low Voltage Programmable Skew Clock Buffer |
| CY7B991V-5JXIT | Low Voltage Programmable Skew Clock Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7B991V-5JI | 功能描述:鎖相環(huán) - PLL 3.3V 80MHz 8 TTL IND Programable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY7B991V-5JIT | 制造商:Cypress Semiconductor 功能描述:Zero Delay Programmable PLL Clock Buffer Single 15MHz to 80MHz 32-Pin PLCC T/R 制造商:Cypress Semiconductor 功能描述:ROBOCLOCK - Tape and Reel |
| CY7B991V-5JXC | 功能描述:鎖相環(huán) - PLL 3.3V 80MHz 8 TTL COM Programable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY7B991V-5JXCT | 功能描述:鎖相環(huán) - PLL 3.3V 80MHz 8 TTL COM Programable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY7B991V-5JXI | 功能描述:鎖相環(huán) - PLL 3.3V 80MHz 8 TTL IND Programable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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