- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378490 > CY7B991V-5JCT (CYPRESS SEMICONDUCTOR CORP) Low Voltage Programmable Skew Clock Buffer PDF資料下載
參數(shù)資料
| 型號： | CY7B991V-5JCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Low Voltage Programmable Skew Clock Buffer |
| 中文描述： | 7B SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大小： | 293K |
| 代理商： | CY7B991V-5JCT |
CY7B991V
3.3V RoboClock
Document Number: 38-07141 Rev. *C
Page 11 of 14
Switching Characteristics – 5 Option
Over the Operating Range
[2, 10]
Parameter
Description
CY7B991V–5
Typ
Unit
Min
15
25
40
5.0
5.0
Max
30
50
80
f
NOM
Operating Clock Frequency in MHz
FS = LOW
[1, 2]
FS = MID
[1, 2]
FS = HIGH
[1, 2]
MHz
t
RPWH
t
RPWL
t
U
t
SKEWPR
t
SKEW0
t
SKEW1
t
SKEW2
t
SKEW3
t
SKEW4
t
DEV
t
PD
t
ODCV
t
PWH
t
PWL
t
ORISE
t
OFALL
t
LOCK
t
JR
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
Zero Output Matched-Pair Skew (XQ0, XQ1)
[14, 15]
Zero Output Skew (All Outputs)
[[14, 15]
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)
[14, 18]
Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)
[14, 18]
Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)
14, 18]
Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)
14, 18]
Device-to-Device Skew
[13, 19]
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation
[20]
Output HIGH Time Deviation from 50%
[21]
Output LOW Time Deviation from 50%
[21]
Output Rise Time
[21, 22]
Output Fall Time
[21, 22]
PLL Lock Time
[22]
Cycle-to-Cycle Output Jitter
ns
ns
See
Table 1
0.1
0.25
0.6
0.5
0.5
0.5
0.25
0.5
0.7
1.0
0.7
1.0
1.25
+0.5
+1.0
2.5
3
1.5
1.5
0.5
25
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
–0.5
–1.0
0.0
0.0
0.15
0.15
1.0
1.0
RMS
[13]
Peak-to-Peak
[13]
Notes
11. Test measurement levels for the CY7B991V are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2 ns or less and output loading as shown
in the AC Test Loads and Waveforms unless otherwise specified.
12.Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
13.SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same t
U
delay has been selected when all are
loaded with 30 pF and terminated with 50
Ω
to V
/2 (CY7B991V).
14.t
SKEWPR
is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0t
.
15.t
SKEW0
is defined as the skew between outputs when they are selected for 0t
U
. Other outputs are divided or inverted but not shifted.
16.C
=30 pF, t
=0.35 ns.
17.There are three classes of outputs: Nominal (multiple of t
U
delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2
or Divide-by-4 mode).
18.t
DEV
is the output-to-output skew between any two devices operating under the same conditions (V
ambient temperature, air flow, etc.)
19.t
is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in t
and t
specifications.
20.Specified with outputs loaded with 30 pF for the CY7B991V–5 and –7 devices. Devices are terminated through 50
Ω
to V
CC
/2.t
PWH
is measured at 2.0V. t
PWL
is
measured at 0.8V.
21.t
ORISE
and t
measured between 0.8V and 2.0V.
22.t
is the time that is required before synchronization is achieved. This specification is valid only after V
CC
is stable and within normal operating limits. This parameter is
measured from the application of a new signal or frequency at REF or FB until t
PD
is within specified limits.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7B991V-5JIT | Low Voltage Programmable Skew Clock Buffer |
| CY7B991V-5JXC | Low Voltage Programmable Skew Clock Buffer |
| CY7B991V-5JXCT | Low Voltage Programmable Skew Clock Buffer |
| CY7B991V-5JXI | Low Voltage Programmable Skew Clock Buffer |
| CY7B991V-5JXIT | Low Voltage Programmable Skew Clock Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7B991V-5JI | 功能描述:鎖相環(huán) - PLL 3.3V 80MHz 8 TTL IND Programable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY7B991V-5JIT | 制造商:Cypress Semiconductor 功能描述:Zero Delay Programmable PLL Clock Buffer Single 15MHz to 80MHz 32-Pin PLCC T/R 制造商:Cypress Semiconductor 功能描述:ROBOCLOCK - Tape and Reel |
| CY7B991V-5JXC | 功能描述:鎖相環(huán) - PLL 3.3V 80MHz 8 TTL COM Programable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY7B991V-5JXCT | 功能描述:鎖相環(huán) - PLL 3.3V 80MHz 8 TTL COM Programable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY7B991V-5JXI | 功能描述:鎖相環(huán) - PLL 3.3V 80MHz 8 TTL IND Programable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。