參數(shù)資料
型號(hào): CY7B991V-5JCT
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): 時(shí)鐘及定時(shí)
英文描述: Low Voltage Programmable Skew Clock Buffer
中文描述: 7B SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32
封裝: PLASTIC, LCC-32
文件頁(yè)數(shù): 4/14頁(yè)
文件大?。?/td> 293K
代理商: CY7B991V-5JCT
CY7B991V
3.3V RoboClock
Document Number: 38-07141 Rev. *C
Page 4 of 14
Test Mode
The TEST input is a three level input. In normal system
operation, this pin is connected to ground, allowing the
CY7B991V to operate as explained in the
“Block Diagram
Description”
on page 3. For testing purposes, any of the three
level inputs can have a removable jumper to ground or be tied
LOW through a 100W resistor. This enables an external tester to
change the state of these pins.
If the TEST input is forced to its MID or HIGH state, the device
operates with its internal phase locked loop disconnected, and
input levels supplied to REF directly controls all outputs. Relative
output to output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW), all outputs
function based only on the connection of their own function select
inputs (xF0 and xF1) and the waveform characteristics of the
REF input.
Figure 1. Typical Outputs with Fb Connected to a Zero Skew Output Test Mode
[4]
t
0
U
t
0
U
t
0
U
t
0
U
t
0
U
t
0
U
t
0
t
0
+
U
t
0
t
0
t
0
t
0
t
0
+
U
+
U
+
U
+
U
+
U
FBInput
REFInput
– 6t
U
– 4t
U
– 3t
U
– 2t
U
– 1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
+6t
U
DIVIDED
INVERT
LM
LH
(N/A)
ML
(N/A)
MM
(N/A)
MH
(N/A)
HL
HM
LL/HH
HH
3Fx
4Fx
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
(N/A)
(N/A)
(N/A)
1Fx
2Fx
Note
4. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 = MID).
相關(guān)PDF資料
PDF描述
CY7B991V-5JIT Low Voltage Programmable Skew Clock Buffer
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CY7B991V-5JXI Low Voltage Programmable Skew Clock Buffer
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