參數(shù)資料
型號: CY3950Z676-125MBI
廠商: Cypress Semiconductor Corp.
英文描述: CPLDs at FPGA Densities
中文描述: CPLD器件在FPGA的密度
文件頁數(shù): 46/86頁
文件大小: 1212K
代理商: CY3950Z676-125MBI
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 46 of 86
Table 9. Mode Select (MSEL) Pin Connectivity Table
Table 10. I/O Banks for Global Clock and Global Control
Pins (in all densities and packages)
Reconfig
TCLK
TDI
TDO
TMS
V
CC
V
CCIO0
V
CCIO1
V
CCIO2
V
CCIO3
V
CCIO4
V
CCIO5
V
CCIO6
V
CCIO7
V
CCJTAG
V
CCCNFG
V
CCPLL[18]
V
CCPRG
Config_Done
CCLK
CCE
Data
Reset
Input
Input
Input
Output
Input
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Output
Output
Output
Input
Output
Pin to start configuration of Delta39K
JTAG Test Clock
JTAG Test Data In
JTAG Test Data Out
JTAG Test Mode Select
Operating Voltage
V
CC
for I/O bank 0
V
CC
for I/O bank 1
V
CC
for I/O bank 2
V
CC
for I/O bank 3
V
CC
for I/O bank 4
V
CC
for I/O bank 5
V
CC
for I/O bank 6
V
CC
for I/O bank 7
V
CC
for JTAG pins
V
CC
for Configuration port
V
CC
for PLL
V
CC
for programming the Self-Boot solution embedded boot PROM
Flag indicating that configuration is complete
Configuration Clock for serial interface with the external boot PROM
Chip select for the external boot PROM (active low)
Pin to receive configuration data from the external boot PROM
Reset signal to interface with the external boot PROM
Table 8. Pin Definition Table
Pin Name
Function
Description
GND
V
CCCNFG
Delta39K - Self-Boot Solution
Delta39K - with external boot PROM
GCLK[0]
GCTL[0]
0
GCLK[1]
GCTL[1]
5
GCLK[2]
GCTL[2]
6
GCLK[3]
GCTL[3]
7
Bank
Number
Table 11. 208 EQFP/PQFP Pin Table
Pin
1
2
3
4
5
6
7
8
9
10
11
CY39030
GCTL0
GND
GCLK0
GND
IO0
IO0
IO0
IO/V
REF0
IO0
IO0
V
CCIO0
CY39050
GCTL0
GND
GCLK0
GND
IO0
IO0
IO0
IO/V
REF0
IO0
IO0
V
CCIO0
CY39100
GCTL0
GND
GCLK0
GND
IO0
IO0
IO0
IO/V
REF0
IO0
IO0
V
CCIO0
CY39165
GCTL0
GND
GCLK0
GND
IO0
IO0
IO0
IO/V
REF0
IO0
IO0
V
CCIO0
CY39200
GCTL0
GND
GCLK0
GND
IO0
IO0
IO0
IO/V
REF0
IO0
IO0
V
CCIO0
Note:
18. The PLL is available in Delta39K ‘V’ devices (2.5V/3.3V) and not in Delta39K ‘Z’ devices (1.8V). In Delta39K ‘Z’ devices, connect V
CCPLL
to V
CC
.
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