參數(shù)資料
型號(hào)： CY37512P352-83BGC
英文描述： Electrically-Erasable Complex PLD
中文描述： 電可擦除復(fù)雜可編程邏輯器件
文件頁數(shù)： 16/66頁
文件大?。?/td> 2069K
代理商： CY37512P352-83BGC
Ultra37000 CPLD Family
Ultra37000: December 13, 1996
Revision: March 15, 2001
16
3.3V Device Characteristics
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65
°
C to +150
°
C
Ambient Temperature with
Power Applied.............................................–55
°
C to +125
°
C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State................................................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
DC Program Voltage.............................................3.0 to 3.6V
Current into Outputs......................................................8 mA
Static Discharge Voltage ...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
[2]
Range
Ambient Temperature
[2]
0°C to +70°C
–40°C to +85°C
–55°C to +125°C
Junction Temperature
0°C to +90°C
–40°C to +105°C
–55°C to +130°C
V
CC
Commercial
Industrial
Military
[3]
3.3V
±
0.3V
3.3V
±
0.3V
3.3V
±
0.3V
3.3V Device Electrical Characteristics
Over the Operating Range
Parameter
V
OH
Description
Test Conditions
I
OH
= –4 mA (Com’l)
[4]
I
OH
= –3 mA (Mil)
[4]
I
OL
= 8 mA (Com’l)
[4]
I
OL
= 6 mA (Mil)
[4]
Min.
2.4
Max.
Unit
V
Output HIGH Voltage
V
CC
= Min.
V
OL
Output LOW Voltage
V
CC
= Min.
0.5
V
V
IH
Input HIGH Voltage
Guaranteed Input Logical HIGH Voltage for
all Inputs
[7]
Guaranteed Input Logical LOW Voltage for
all Inputs
[7]
V
I
= GND OR V
CC
, Bus-Hold Disabled
V
O
= GND or V
CC
, Output Disabled,
Bus-Hold Disabled
V
CC
= Max., V
OUT
= 0.5V
V
CC
= Min., V
IL
= 0.8V
2.0
5.5
V
V
IL
Input LOW Voltage
–0.5
0.8
V
I
IX
I
OZ
Input Load Current
Output Leakage Current
–10
–50
10
50
μ
A
μ
A
I
OS
I
BHL
Output Short Circuit Current
[8, 5]
Input Bus-Hold LOW Sustaining
Current
Input Bus-Hold HIGH Sustaining
Current
Input Bus-Hold LOW Overdrive
Current
Input Bus-Hold HIGH Overdrive
Current
–30
+75
–160
mA
μ
A
I
BHH
V
CC
= Min., V
IH
= 2.0V
–75
μ
A
I
BHLO
V
CC
= Max.
+500
μ
A
I
BHHO
V
CC
= Max.
–500
μ
A
Inductance
[5]
Parameter
L
Description
Maximum Pin
Inductance
Test
Conditions
V
IN
= 3.3V
at f = 1 MHz
44-
Lead
TQFP
2
44-
Lead
PLCC
5
44-
Lead
CLCC
2
84-
Lead
PLCC
8
84-
Lead
CLCC
5
100-
Lead
TQFP
8
160-
Lead
TQFP
9
208-
Lead
PQFP
11
Unit
nH
相關(guān)PDF資料
PDF描述
CY37512VP256-66BGI Electrically-Erasable Complex PLD
CY37512VP352-66BGI Electrically-Erasable Complex PLD
CY37032VP Programmable Logic
CY37032VP44-143AC
CY37032VP48-100BAC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY37512P352-83BGI 制造商:Cypress Semiconductor 功能描述:CPLD Ultra37000 Family 15K Gates 512 Macro Cells 83MHz 5V 388-Pin BGA 制造商:Cypress Semiconductor 功能描述:CPLD Ultra37000 Family 15K Gates 512 Macro Cells 83MHz CMOS Technology 5V 388-Pin BGA
CY37512VP208-66NC 制造商:Cypress Semiconductor 功能描述:CPLD Ultra37000 Family 15K Gates 512 Macro Cells 66MHz 3.3V 208-Pin PQFP
CY37512VP208-66NI 制造商:Cypress Semiconductor 功能描述:
CY37512VP208-66NXI 功能描述:IC CPLD 512 MACROCELL 208BQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:Ultra37000™ 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤
CY37512VP208-83NC 制造商:Cypress Semiconductor 功能描述:CPLD Ultra37000 Family 15K Gates 512 Macro Cells 83MHz CMOS Technology 3.3V 208-Pin PQFP
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*