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| 型號： | CY37128VP84-83YMB |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | EE PLD, 15 ns, CQCC84 |
| 封裝： | CERAMIC, LCC-84 |
| 文件頁數(shù)： | 34/66頁 |
| 文件大小： | 1259K |
| 代理商： | CY37128VP84-83YMB |
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Ultra37000 CPLD Family
4
Architecture Overview of Ultra37000 Family
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) consists of a
completely global routing matrix for signals from I/O pins and
feedbacks from the logic blocks. The PIM provides extremely
robust interconnection to avoid fitting and density limitations.
The inputs to the PIM consist of all I/O and dedicated input pins
and all macrocell feedbacks from within the logic blocks. The
number of PIM inputs increases with pin count and the number
of logic blocks. The outputs from the PIM are signals routed to
the appropriate logic blocks. Each logic block receives 36 in-
puts from the PIM and their complements, allowing for 32-bit
operations to be implemented in a single pass through the
device. The wide number of inputs to the logic block also im-
proves the routing capacity of the Ultra37000 family.
An important feature of the PIM is its simple timing. The prop-
agation delay through the PIM is accounted for in the timing
specifications for each device. There is no additional delay for
traveling through the PIM. In fact, all inputs travel through the
PIM. As a result, there are no route-dependent timing param-
eters on the Ultra37000 devices. The worst-case PIM delays
are incorporated in all appropriate Ultra37000 specifications.
Routing signals through the PIM is completely invisible to the
user. All routing is accomplished by software—no hand routing
is necessary. Warp and third-party development packages
automatically route designs for the Ultra37000 family in a mat-
ter of minutes. Finally, the rich routing resources of the
Ultra37000 family accommodate last minute logic changes
while maintaining fixed pin assignments.
Logic Block
The logic block is the basic building block of the Ultra37000
architecture. It consists of a product term array, an intelligent
product-term allocator, 16 macrocells, and a number of I/O
cells. The number of I/O cells varies depending on the device
used. Refer to Figure 1 for the block diagram.
Product Term Array
Each logic block features a 72 x 87 programmable product
term array. This array accepts 36 inputs from the PIM, which
originate from macrocell feedbacks and device pins. Active
LOW and active HIGH versions of each of these inputs are
generated to create the full 72-input field. The 87 product
terms in the array can be created from any of the 72 inputs.
Of the 87 product terms, 80 are for general-purpose use for the
16 macrocells in the logic block. Four of the remaining seven
product terms in the logic block are output enable (OE) product
terms. Each of the OE product terms controls up to eight of the
16 macrocells and is selectable on an individual macrocell ba-
sis. In other words, each I/O cell can select between one of two
OE product terms to control the output buffer. The first two of
these four OE product terms are available to the upper half of
the I/O macrocells in a logic block. The other two OE product
terms are available to the lower half of the I/O macrocells in a
logic block.
The next two product terms in each logic block are dedicated
asynchronous set and asynchronous reset product terms. The
final product term is the product term clock. The set, reset, OE
and product term clock have polarity control to realize OR
functions in a single pass through the array.
Figure 1. Logic Block with 50% Buried Macrocells
I/O
CELL
0
PRODUCT
TERM
ALLOCATOR
I/O
CELL
14
MACRO-
CELL
0
MACRO-
CELL
1
MACRO-
CELL
14
0
16
PRODUCT
TERMS
72 x 87
PRODUCT TERM
ARRAY
80
36
8
16
TO
PIM
FROM
PIM
7
3
2
MACRO-
CELL
15
2
to cells
2, 4, 6 8, 10, 12
0
16
PRODUCT
TERMS
0
16
PRODUCT
TERMS
0
16
PRODUCT
TERMS
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