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| 型號(hào)： | CY292510 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大?。?/td> | 72K |
| 代理商： | CY292510 |
CY292510
Document #: 38-07472 Rev. **
Page 3 of 6
Table 5. Recommended Operating Conditions
Parameter
Description
Min.
3.0
3.0
0
–
–
0
Typ.
3.3
3.3
Max.
3.6
3.6
V
DD
–
12
12
85
Unit
V
V
V
mA
mA
°
C
V
DD
V
DDA
V
IN
I
OH
I
OL
T
A
Supply voltage
Analog supply voltage
Voltage applied to input pins
High level output current
Low level output current
Operating free-air temperature
–
–
–
Table 6. DC Parameters
(V
DD
= V
DDA
= 3.3V ±10%, T
A
= 0
°
C to +85
°
C)
Parameter
Description
V
IH
HIGH Level input voltage
V
IL
LOW level input voltage
V
OH
HIGH level output voltage
Test Conditions
Min.
2.0
Typ.
Max.
Unit
V
V
0.8
Min. to Max.
V
DD
= 3V
V
DD
= 3V
Min. to Max.
V
DD
= 3V
V
DD
= 3V
V
DD
= 3.135V
V
DD
= 3.3V
V
DD
= 3.465V
V
DD
= 3.135V
V
DD
= 3.3V
V
DD
= 3.465V
V
DD
= 3V
I
OH
=
–
100
μ
A
I
OH
=
–
12 mA
I
OH
= -6 mA
I
OL
=100
μ
A
I
OL
= 12 mA
I
OL
= 6 mA
V
O
= 1V
V
O
= 1.65V
V
O
= 3.135V
V
O
= 1.95V
V
O
= 1.65V
V
O
= 0.4V
I
IN
=
–
18 mA
V
I
= V
DD
or V
SS
V
DD
–
0.2
2.1
2.4
V
V
OL
LOW level output voltage
0.2
0.8
0.55
V
I
OH
HIGH level output current
–
32
mA
–
36
–
12
I
OL
LOW level output current
34
mA
40
14
–
1.2
±5
3.5
5
V
IK
I
I
I
DDA
I
DDQ
I
DDQ
Clamp voltage
Input leakage current per pin V
DD
= 3.6V
PLL supply current
Quiescent supply current
Change in quiescent current V
DD
= 3.3 V to 3.6V One input at V
DD
–
0.6V,
V
μ
A
mA
mA
Min. to Max.
V
DD
= 3.6V
2.3
I
O
= 0 V
IN
= V
DD
or V
SS
other inputs at V
DD
or
V
SS
Outputs loaded at 133 MHz
500
μ
A
I
DD
Dynamic supply current
V
DD
= 3.6V
200
mA
Table 7. AC Parameters
(V
DD
= V
DDA
= 3.3V ±10%, T
A
= 0
°
C to +85
°
C)
[6, 7, 8, 9, 10]
Parameter
From Input/Condition
Reference Clock
Reference Clock
Output Operating Frequency
To Output
V
DD
= 3.3V ± 0.3V
Min.
25
40
25
25
–
125
Unit
MHz
%
Typ.
Max.
200
60
185
200
125
Fin
Duty Cycle
Fout
30-pF load
25-pF load
FBIN
MHz
tPHASE error
[11]
, static
offset (normalized)
Duty Cycle
REF = 66 to 166 MHz
pS
Any clock out or FBOUT
45
55
%
Notes:
6.
7.
8.
9.
10. OE = V
.
11.
Uses the averaging feature of the scope to remove the jitter component.
Parameters are guaranteed by design and characterization and are not 100% production tested.
The tSK(0) specification is only valid for equal loading of all outputs (30 pF//500
) for Fout < 185 MHz and (25 pF//500
) for Fout > 185 MHz.
for Fout < 185 MHz and 25 pF//500
for Fout > 185 MHz.
The test load is 30 pF//500
Figure 2
.
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|---|---|
| CY29350 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5V or 3.3V, 200-MHz, 9-Output Clock Driver |
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