參數(shù)資料
型號： CY292510
英文描述： Clocks and Buffers
中文描述： 時鐘和緩沖器
文件頁數(shù)： 2/6頁
文件大小： 72K
代理商： CY292510
CY292510
Document #: 38-07472 Rev. **
Page 2 of 6
Pin Description
Notes:
2.
Stresses beyond those listed under
“
absolute maximum ratings
”
may cause permanent damage to the device. These are stresses rating only and functional
operation of the device at these or any other conditions beyond those indicated under
“
recommended operating conditions
”
is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The maximum package power dissipation is calculated using a junction temperature or 150
°
C and board trace length of 750 mils.
Unused inputs must be held high or low to prevent them from floating.
3.
4.
5.
Pin
Name
REF
FBOUT
FBIN
I/O
Description
24
12
13
I
O
I
Input reference pin.
Feedback Output. Not affected by the OE pin.
This pin is to be connected to the FBOUT pin. A timing delay may be inserted to change the
delay through the device.
Output Enable clock (high active). OE low places CLK(0:9) into low state. See
Block Diagram.
PWR 3.3V supply for core logic, inputs and outputs.
PWR Power for internal analog circuitry. This supply should have separate de coupling. For test
purposes, when V
DDA
is strapped to ground the internal PLL is shut off and bypassed and
REF is buffered directly to device outputs( see
Table 4
).
O
Low skew clock outputs. Outputs enabled by OE in high state.
11
2, 10, 14, 22
23
OE
V
DD
V
DDA
I
3, 4, 5, 8, 9, 15,
16, 17, 20, 21
6, 7, 18, 19
1
1Y(0:9)
V
SS
V
SSA
PWR Ground pins for the core logic and I/Os.
PWR Ground pin for analog circuitry.
Table 2. Absolute Maximum Ratings
[2]
Parameter
Description
Commercial
Unit
V
V
V
mA
mA
mA
mA
W
°
C
V
DD
, V
DDA
V
I[3]
V
O[3]
I
IK
(VI<0)
I
OK
(V
O
<0 or V
O
>V
DD
I
O
(V
O
= 0 to V
DD
)
V
DD
or V
SS
T
A
= 50
°
C (in still air)
[4]
Maximum power dissipation
T
STG
Storage Temperature Range
Supply Voltage Range
Input Voltage Range
Voltage range applied to any output in the high or low state
–
0.5 to V
DD
+0.5
Input clamp current
Terminal voltage with respect to V
SS
(inputs V
IH
2.5, V
IL
2.5 ±50
Continuous Output Current
Continuous Current
–
0.5 to +4.6
–
0.5 to V
DD
+ 0.5
–
50
±50
±100
0.7
–
65
°
C to +150
°
C
Table 3. Capacitance
[5]
Parameter
Description
Min.
–
–
Typ.
5
6
Max.
–
–
Unit
pF
pF
C
IN
C
O
Input Capacitance V
IN
= V
DD
or V
SS
Output Capacitance V
O
= V
DD
or V
SS
Table 4. Test Mode Table (V
DDA
= 0V)
INPUTS
OUTPUTS
OE
LOW
LOW
HIGH
HIGH
REF
LOW
HIGH
LOW
HIGH
1Y(0:9)
LOW
LOW
LOW
HIGH
FBOUT
LOW
HIGH
LOW
HIGH
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