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參數(shù)資料
| 型號(hào)： | CY26503 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 2/13頁(yè) |
| 文件大?。?/td> | 161K |
| 代理商： | CY26503 |
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CY26501/CY26502
Document #: 38-07356 Rev. *A
Page 2 of 13
Pin Definitions
Pin Name
REFCLK
Pin
No.
2
Pin
Type
I
Pin Description
Reference Clock Input:
Reference clock input, normally supplied by a system
frequency synthesizer (Cypress W133).
Phase Detector Input:
The phase difference between this signal and SYNCLKN
is used to synchronize the Rambus Channel Clock with the system clock. Both
PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory con-
troller. If Gear Ratio Logic is not used, this pin would be connected to Ground.
Phase Detector Input:
The phase difference between this signal and PCLKM is
used to synchronize the Rambus Channel Clock with the system clock. Both
PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory con-
troller. If Gear Ratio Logic is not used, this pin would be connected to Ground.
Clock Output Enable:
When this input is driven to active LOW, it disables the
differential Rambus Channel clocks.
Active LOW Power-Down:
When this input is driven to active LOW, it disables
the differential Rambus Channel clocks and places the CY26501/CY26502 in pow-
er-down mode.
PLL Multiplier Select:
These inputs select the PLL prescaler and feedback divid-
ers to determine the multiply ratio for the PLL for the input REFCLK:
PCLKM
6
I
SYNCLKN
7
I
STOPB
11
I
PWRDNB
12
I
MULT 0:1
15, 14
I
CLK, CLKB
S0, S1
20, 18
24, 23
O
I
Complementary Output Clock:
Differential Rambus Channel clock outputs.
Mode Control Input:
These inputs control the operating mode of the
CY26501/CY26502:
NC
VDDIR
VDDIPD
19
1
10
-
No Connect
Reference for REFCLK:
Voltage reference for input reference clock.
Reference for Phase Detector:
Voltage reference for phase detector inputs and
STOPB.
Power Connection:
Power supply for core logic and output buffers. Connected to
3.3V supply.
Ground Connection:
Connect all ground pins to the common system ground
plane.
RefV
RefV
VDD
3, 9, 16, 22
P
GND
4, 5, 8, 13,
17, 21
G
MULT1
0
1
1
0
MULT0
0
0
1
1
CY26501
PLL/REFCLK
4.5
6
8
5.333
CY26502
PLL/REFCLK
4
6
8
5.333
S1
0
1
0
1
S0
0
0
1
1
MODE
Normal
Output Enable Test
Bypass
Test
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| CY2651-000 | 制造商:TE Connectivity 功能描述:SLC41AC-1406A - Bulk 制造商:TE CONNECTIVITY 功能描述:SLC41AC-1406A |
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| CY2654-000 | 制造商:TE Connectivity 功能描述:SLC41AC-2010A - Bulk 制造商:TE CONNECTIVITY 功能描述:SLC41AC-2010A |
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