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參數(shù)資料
| 型號(hào)： | CY26503 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 161K |
| 代理商： | CY26503 |
CY26501/CY26502
Document #: 38-07356 Rev. *A
Page 10 of 13
Notes:
7.
8.
9.
Output Jitter spec measured at t
CYCLE
= 1.87 ns. (Commercial Temperature)
V
COS
= V
OH
–
V
OL.
r
OUT
=
V
O
/
I
O
. This is defined at the output pins.
Table 14. Device Characteristics
Parameter
t
CYCLE
Clock Cycle Time (Commercial temperature)
t
CYCLE
Clock Cycle Time (Industrial temperature)
t
J
t
STEP
Phase Aligner Phase Step Size (at Clk/ClkB)
t
ERR,PD
Phase Detector Phase Error for Distributed Loop Measured at PclkM-
SynclkN (rising edges) (does not include clock jitter)
t
ERR,SSC
PLL Output Phase Error when Tracking SSC
V
X,STOP
Output Voltage during Clk Stop (StopB=0)
V
X
Differential Output Crossing-Point Voltage
V
COS
V
OH
Output High Voltage
V
OL
Output Low voltage
r
OUT
I
OZ
Output Current during Hi-Z (S0 = 0, S1 = 1)
I
OZ,STOP
Output Current during Clk Stop (StopB = 0)
DC
Output Duty Cycle over 10,000 Cycles
t
DC,ERR
Output Cycle-to-Cycle Duty Cycle Error
t
R,
t
F
Output Rise and Fall Times (measured at 20%-80% of output voltage)
t
CR,CF
Difference between Output Rise and Fall Times on the Same Pin of a
Single Device (20%-80%)
Description
Min.
1.87
2.5
-
1
–
100
Max.
3.75
3.75
50
-
100
Unit
ns
ns
ps
ps
ps
Cycle-to-Cycle Jitter at Clk/ClkB
[7]
–
100
1.1
1.3
0.8
-
0.8
12
-
-
40
-
150
-
100
2.0
1.8
1.2
2.2
-
50
50
500
60
50
400
100
ps
V
V
V
V
V
μA
μA
Output Voltage Swing (p-p single-ended)
[8]
Output Dynamic Resistance (at pins)
[9]
%t
CYCLE
ps
ps
ps
Ordering Information
Ordering Code
CY26501PVI
CY26501PVC
CY26502PVI
CY26502PVC
Package Type
24-pin SSOP (150 mils)
Temperature Range
I = Industrial
C = Commercial
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