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參數(shù)資料
| 型號： | CY24210 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大小： | 150K |
| 代理商： | CY24210 |
CY24239
Document #: 38-07038 Rev. **
Page 6 of 15
Writing Data Bytes
Each bit in Data Bytes 0
–
7 controls a particular device function
except for the
“
reserved
”
bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit 7.
Table 5
gives the bit formats for registers located in Data Bytes
0
–
7.
Table 6
details additional frequency selections that are avail-
able through the serial data interface.
Table 7
details the select functions for Byte 0, bits 1 and 0.
Table 5. Data Bytes 0
–
7 Serial Configuration Map
Affected Pin
Pin No.
Pin Name
Data Byte 0
7
--
6
--
5
--
4
--
3
--
Bit(s)
Control Function
Bit Control
Default
0
1
--
--
--
--
--
(Reserved)
SEL2
SEL1
SEL0
Frequency Table Selection
--
--
0
0
0
0
0
Refer to
Table 6
Refer to
Table 6
Refer to
Table 6
Frequency Con-
trolled by FS(3:0)
Ta-
ble 2
Frequency Con-
trolled by SEL(3:0)
Table 6
Refer to
Table 6
2
1
0
--
--
--
--
--
SEL3
(Reserved)
--
0
0
0
--
--
Test Mode
Normal
Three-stated
Data Byte 1
7
6
5
4
3
2
1
0
Data Byte 2
7
6
5
4
3
2
1
0
Data Byte 3
7
6
5
4
3
--
--
--
--
46
49
51
52
--
--
--
--
--
--
--
--
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
--
--
--
--
--
--
--
--
0
0
0
0
1
1
1
1
SDRAM16
CPU2
CPU1
CPU_F
LOW
LOW
LOW
LOW
Active
Active
Active
Active
--
8
16
14
13
12
11
9
--
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
--
--
0
1
1
1
1
1
1
1
PCI_F
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Active
Active
Active
Active
Active
Active
Active
--
--
29
30
--
--
(Reserved)
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
--
--
--
--
0
0
1
1
1
48MHz
24MHz
SDRAM12:15
LOW
LOW
LOW
Active
Active
Active
33, 32,
25, 24
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