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參數(shù)資料
| 型號： | CY24210 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 150K |
| 代理商： | CY24210 |
CY24239
Document #: 38-07038 Rev. **
Page 12 of 15
SDRAM 0:16 Clock Outputs (Lump Capacitance Test Load = 22 pF)
Parameter
t
P
t
H
t
L
t
R
Description
Period
High Time
Low Time
Output Rise Edge
Rate
Output Fall Edge
Rate
Duty Cycle
Test Condition/
Comments
SDRAMIN =
100 MHz
Typ.
Unit
ns
ns
ns
V/ns
Min.
10
3.0
2.0
1
Max.
10.5
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
4
t
F
Measured from 2.4V to 0.4V
1
4
V/ns
t
D
Measured on rising and falling edge at
1.5V
Measured on rising and falling edge at
1.5V
Measured from SDRAMIN
45
55
%
t
SK
Output Skew
250
ps
t
PD
Propagation
Delay
AC Output
Impedance
3.7
ns
Z
o
Average value during switching transi-
tion. Used for determining series termi-
nation value.
15
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
f
Frequency, Actual
f
D
Deviation from 48 MHz
m/n
PLL Ratio
t
R
Output Rise Edge Rate
t
F
Output Fall Edge Rate
t
D
Duty Cycle
f
ST
Frequency Stabilization
from Power-up (cold start)
Test Condition/Comments
Determined by PLL divider ratio (see m/n below)
(48.008
–
48)/48
(14.31818 MHz x 57/17 = 48.008 MHz)
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to fre-
quency stabilization.
Average value during switching transition. Used
for determining series termination value.
Min.
Typ.
48.008
+167
57/17
Max.
Unit
MHz
ppm
0.5
0.5
45
2
2
V/ns
V/ns
%
ms
55
3
Z
o
AC Output Impedance
25
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