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參數(shù)資料
| 型號： | CY2308SI-4 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V Zero Delay Buffer |
| 中文描述： | 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 0.150 INCH, MS-012, SOIC-16 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 374K |
| 代理商： | CY2308SI-4 |
CY2308
Document Number: 38-07146 Rev. *E
Page 3 of 15
Zero Delay and Skew Control
To close the feedback loop of the CY2308, the FBK pin is driven
from any of the eight available output pins. The output driving the
FBK pin drives a total load of 7 pF plus any additional load that
it drives. The relative loading of this output to the remaining
outputs adjusts the input-output delay. This is shown in the
For applications requiring zero input-output delay, all outputs
including the one providing feedback is equally loaded.
If input-output delay adjustments are required, use the Zero
Delay and Skew Control graph to calculate loading differences
between the feedback output and remaining outputs.
For zero output-output skew, outputs are loaded equally. For
further information on using CY2308, refer to the application note
“CY2308: Zero Delay Buffer.”
Available CY2308 Configurations
Device
Feedback From
Bank A Frequency
Bank B Frequency
CY2308–1
Bank A or Bank B
Reference
CY2308–1H
Bank A or Bank B
Reference
CY2308–2
Bank A
Reference
Reference/2
CY2308–2
Bank B
2 X Reference
Reference
CY2308–3
Bank A
2 X Reference
Reference or Reference[5]
CY2308–3
Bank B
4 X Reference
2 X Reference
CY2308–4
Bank A or Bank B
2 X Reference
CY2308–5H
Bank A or Bank B
Reference /2
Table 2. REF. Input to CLKA/CLKB Delay Versus Difference in Loading between FBK pin and CLKA/CLKB Pins
Note
5. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY2308–2.
相關(guān)PDF資料 |
PDF描述 |
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| CY2308 | 3.3V Zero Delay Buffer |
| CY2309AZI-1H | 2309 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| CY23S09SXC-1T | 23S SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| CY2DP818ZXCT | 2DP SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO38 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2308SI-4T | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Driver Single 10MHz to 133MHz 16-Pin SOIC T/R |
| CY2308SI-5H | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Driver Single 10MHz to 133MHz 16-Pin SOIC |
| CY2308SXC-1 | 功能描述:時鐘緩沖器 3.3VZDB COM RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY2308SXC-1H | 功能描述:時鐘緩沖器 3.3VZDB COM RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY2308SXC1HT | 制造商:Cypress Semiconductor 功能描述: |
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