參數(shù)資料
型號： CY2308SI-4
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 時鐘及定時
英文描述： 3.3V Zero Delay Buffer
中文描述： 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封裝： 0.150 INCH, MS-012, SOIC-16
文件頁數(shù)： 11/15頁
文件大?。?/td> 374K
代理商： CY2308SI-4
CY2308
Document Number: 38-07146 Rev. *E
Page 5 of 15
Switching Characteristics for Commercial Temperature Devices [8]
Parameter
Name
Test Conditions
Min.
Typ.
Max.
Unit
t1
Output Frequency
30-pF load, All devices
10
–
100
MHz
t1
Output Frequency
20-pF load, –1H, –5H devices[9]
10
–
133.3
MHz
t1
Output Frequency
15-pF load, –1, –2, –3, –4 devices
10
–
133.3
MHz
Duty Cycle[7] = t2 ÷ t1
(–1, –2, –3, –4, –1H, –5H)
Measured at 1.4V, FOUT = 66.66 MHz
30-pF load
40.0
50.0
60.0
%
Duty Cycle[7] = t2 ÷ t1
(–1, –2, –3, –4, –1H, –5H)
Measured at 1.4V, FOUT <50.0 MHz
15-pF load
45.0
50.0
55.0
%
t3
Rise Time[7]
(–1, –2, –3, –4)
Measured between 0.8V and 2.0V,
30-pF load
–
2.20
ns
t3
Rise Time[7]
(–1, –2, –3, –4)
Measured between 0.8V and 2.0V,
15-pF load
–
1.50
ns
t3
Rise Time[7]
(–1H, –5H)
Measured between 0.8V and 2.0V,
30-pF load
–
1.50
ns
t4
Fall Time[7]
(–1, –2, –3, –4)
Measured between 0.8V and 2.0V,
30-pF load
–
2.20
ns
t4
Fall Time[7]
(–1, –2, –3, –4)
Measured between 0.8V and 2.0V,
15-pF load
–
1.50
ns
t4
Fall Time[7]
(–1H, –5H)
Measured between 0.8V and 2.0V,
30-pF load
–
1.25
ns
t5
Output to Output Skew on
same Bank
(–1, –2, –3, –4)[7]
All outputs equally loaded
–
200
ps
Output to Output Skew
(–1H, –5H)
All outputs equally loaded
–
200
ps
Output Bank A to Output
Bank B Skew (–1, –4, –5H)
All outputs equally loaded
–
200
ps
Output Bank A to Output
Bank B Skew (–2, –3)
All outputs equally loaded
–
400
ps
t6
Delay, REF Rising Edge to
FBK Rising Edge[7]
Measured at VDD/2
–
0
±250
ps
t7
Device to Device Skew[7]
Measured at VDD/2 on the FBK pins of
devices
–0
700
ps
t8
Output Slew Rate[7]
Measured between 0.8V and 2.0V on –1H,
–5H device using Test Circuit 2
1–
V/ns
tJ
Cycle to Cycle Jitter[7]
(–1, –1H, –4, –5H)
Measured at 66.67 MHz, loaded outputs,
15-pF load
–75
200
ps
Measured at 66.67 MHz, loaded outputs,
30-pF load
––
200
ps
Measured at 133.3 MHz, loaded outputs,
15-pF load
––
100
ps
tJ
Cycle to Cycle Jitter[7]
(–2, –3)
Measured at 66.67 MHz, loaded outputs
30-pF load
––
400
ps
Measured at 66.67 MHz, loaded outputs
15-pF load
––
400
ps
tLOCK
PLL Lock Time[7]
Stable power supply, valid clocks presented
on REF and FBK pins
––
1.0
ms
Notes
8. All parameters are specified with loaded outputs.
9. CY2308–5H has maximum input frequency of 133.33 MHz and maximum output of 66.67 MHz.
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