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參數(shù)資料
| 型號： | CY2308SI-2 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V Zero Delay Buffer |
| 中文描述： | 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 0.150 INCH, MS-012, SOIC-16 |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 503K |
| 代理商： | CY2308SI-2 |
CY2308
Document Number: 38-07146 Rev. *L
Page 6 of 17
tPD
(–1, –2, –3, –4, –1H, –5H)
Measured at 1.4 V, FOUT =
66.66 MHz, 30 pF load
40.0
50.0
60.0
%
tPD
(–1, –2, –3, –4, –1H, –5H)
Measured at 1.4 V, FOUT <
50 MHz, 15 pF load
45.0
50.0
55.0
%
t3
Rise time[10, 12]
(–1, –2, –3, –4)
Measured between 0.8 V and
2.0 V, 30 pF load
–
2.20
ns
t3
Rise time[10, 12]
(–1, –2, –3, –4)
Measured between 0.8 V and
2.0 V, 15 pF load
–
1.50
ns
t3
Rise time[10, 12]
(–1H, –5H)
Measured between 0.8 V and
2.0 V, 30 pF load
–
1.50
ns
t4
Fall time[10, 12]
(–1, –2, –3, –4)
Measured between 0.8 V and
2.0 V, 30 pF load
–
2.20
ns
t4
Fall time[10, 12]
(–1, –2, –3, –4)
Measured between 0.8 V and
2.0 V, 15 pF load
–
1.50
ns
t4
Fall time[10, 12]
(–1H, –5H)
Measured between 0.8 V and
2.0 V, 30 pF load
–
1.25
ns
t5
Output to output skew on same
Bank (–1, –2, –3, –4)[10, 12]
All outputs equally loaded
–
200
ps
Output to output skew (–1H,
–5H)
All outputs equally loaded
–
200
ps
Output Bank A to output Bank
B skew (–1, –4, –5H)
All outputs equally loaded
–
200
ps
Output Bank A to output Bank
B skew (–2, –3)
All outputs equally loaded
–
400
ps
t6
Delay, REF rising edge to FBK
rising edge[10, 12]
Measured at VDD/2
–
0
±250
ps
t7
Device to device skew[10, 12]
Measured at VDD/2 on the FBK
pins of devices
–
0
700
ps
t8
Output slew rate[10, 12]
Measured between 0.8 V and
2.0 V on –1H, –5H device using
Test Circuit 2
1–
V/ns
tJ
Cycle to cycle Jitter[10, 12]
(–1, –1H, –4, –5H)
Measured at 66.67 MHz,
loaded outputs, 15 pF load
–
75
200
ps
Measured at 66.67 MHz,
loaded outputs, 30 pF load
–
200
ps
Measured at 133.3 MHz,
loaded outputs, 15 pF load
–
100
ps
tJ
Cycle to cycle Jitter[10, 12]
(–2, –3)
Measured at 66.67 MHz,
loaded outputs, 30 pF load
–
400
ps
Measured at 66.67 MHz,
loaded outputs, 15 pF load
–
400
ps
tLOCK
PLL lock time[10, 12]
Stable power supply, valid
clocks presented on REF and
FBK pins
––
1.0
ms
Switching Characteristics for Commercial Temperature Devices (continued)
Parameter[9]
Name
Test Conditions
Min
Typ.
Max
Unit
Notes
10. All parameters are specified with loaded outputs.
11. Parameter is guaranteed by design and characterization. Not 100% tested in production.
12. All parameters are specified with loaded outputs.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2308SI-2[19] | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3 V Zero Delay Buffer |
| CY2308SI-2T | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Driver Single 10MHz to 133MHz 16-Pin SOIC T/R |
| CY2308SI-2T[19] | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3 V Zero Delay Buffer |
| CY2308SI-3 | 功能描述:IC CLK ZDB 8OUT 133MHZ 16SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| CY2308SI-3T | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Driver Single 10MHz to 133MHz 16-Pin SOIC T/R 制造商:Rochester Electronics LLC 功能描述:3.3VPLL ZERO DELAY CLOCK MULTIPLEXER SOIC 16 - Bulk |
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