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參數(shù)資料
| 型號： | CY2308SI-2 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V Zero Delay Buffer |
| 中文描述： | 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 0.150 INCH, MS-012, SOIC-16 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 503K |
| 代理商： | CY2308SI-2 |
CY2308
Document Number: 38-07146 Rev. *L
Page 4 of 17
Zero Delay and Skew Control
To close the feedback loop of the CY2308, the user has to
connect any one of the eight available output pins to FBK pin.
The output driving the FBK pin drives a total load of 7 pF plus
any additional load that it drives. The relative loading of this
output to the remaining outputs adjusts the input-output delay as
shown in the Figure 2.
For applications requiring zero input-output delay, all outputs
including the one providing feedback is equally loaded.
If input-output delay adjustments are required, use the Zero
Delay and Skew Control graph to calculate loading differences
between the feedback output and remaining outputs.
For zero output-output skew, outputs are loaded equally. For
further information on using CY2308, refer to the application note
Available CY2308 Configurations
Device
Feedback From[5]
Bank A Frequency
Bank B Frequency
CY2308–1
Bank A or Bank B
Reference
CY2308–1H
Bank A or Bank B
Reference
CY2308–2
Bank A
Reference
Reference/2
CY2308–2
Bank B
2 x Reference
Reference
CY2308–3
Bank A
2 x Reference
Reference[6]
CY2308–3
Bank B
4 x Reference
2 x Reference
CY2308–4
Bank A or Bank B
2 x Reference
CY2308–5H
Bank A or Bank B
Reference /2
Figure 2. REF. Input to CLKA/CLKB Delay Versus Difference in Loading Between FBK Pin and CLKA/CLKB Pins
Notes
5. User has to select one of the available outputs that drive the feedback pin and need to connect selected output pin to FBK pin externally.
6. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use CY2308–2.
相關(guān)PDF資料 |
PDF描述 |
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| CY2308SI-4 | 3.3V Zero Delay Buffer |
| CY2308 | 3.3V Zero Delay Buffer |
| CY2309AZI-1H | 2309 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| CY23S09SXC-1T | 23S SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| CY2DP818ZXCT | 2DP SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO38 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2308SI-2[19] | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3 V Zero Delay Buffer |
| CY2308SI-2T | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Driver Single 10MHz to 133MHz 16-Pin SOIC T/R |
| CY2308SI-2T[19] | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3 V Zero Delay Buffer |
| CY2308SI-3 | 功能描述:IC CLK ZDB 8OUT 133MHZ 16SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| CY2308SI-3T | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Driver Single 10MHz to 133MHz 16-Pin SOIC T/R 制造商:Rochester Electronics LLC 功能描述:3.3VPLL ZERO DELAY CLOCK MULTIPLEXER SOIC 16 - Bulk |
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