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參數(shù)資料
| 型號： | CXK79M72C164GB |
| 英文描述： | MEMORY-SigmaRAM 16Meg 1x1z HSTL I/O (256K x 72) (27 pages 368K Rev. 7/6/01) |
| 中文描述： | 內(nèi)存SigmaRAM 16Meg 1x1z HSTL的I / O（256 × 72）（27頁368K牧師7/6/01） |
| 文件頁數(shù)： | 7/30頁 |
| 文件大?。?/td> | 554K |
| 代理商： | CXK79M72C164GB |
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SONY
Σ
RAM CXK79M72C160GB / CXK79M36C160GB / CXK79M18C160GB
Preliminary
18Mb 1x1Lp, HSTL, rev 1.0
7 / 30
July 19, 2002
Clock Truth Table
Notes
:
1. “1” = input “high”; “0” = input “l(fā)ow”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. “***” indicates that the DQ input requirement or output state and the CQ output state are determined by the previous operation.
3. If E2 = EP2 and E3 = EP3 then E = “T” else E = “F”.
4. If one or more Bx = 0 then B = “T” else B = “F”.
5. DQsaretri-statedinresponsetoBankDeselect,Deselect,andWritecommands,onefullcycleafterthecommandis sampled.
6. CQs are tri-stated in response to Bank Deselect commands only, one full cycle after the command is sampled.
7. Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four
(4) distinct pieces of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal ad-
dress wraps back to the initial external (base) address.
CK
E1
(t
n
)
E
(t
n
)
ADV
(t
n
)
W
(t
n
)
B
(t
n
)
Previous
Operation
Current Operation
DQ/CQ
(t
n
)
DQ/CQ
(t
n+1
)
↑
X
F
0
X
X
X
Bank Deselect
***
Hi-Z
↑
X
X
1
X
X
Bank Deselect
Bank Deselect (Continue)
Hi-Z
Hi-Z
↑
1
T
0
X
X
X
Deselect
***
Hi-Z/CQ
↑
X
X
1
X
X
Deselect
Deselect (Continue)
Hi-Z/CQ
Hi-Z/CQ
↑
0
T
0
0
T
X
Write
Loads new address
Stores DQx if Bx = 0
***
D1/CQ
↑
0
T
0
0
F
X
Write (Abort)
Loads new address
No data stored
***
X/CQ
↑
X
X
1
X
T
Write
Write Continue
Increments address by 1
Stores DQx if Bx = 0
D1/CQ
D2/CQ
↑
X
X
1
X
F
Write
Write Continue (Abort)
Increments address by 1
No data stored
D1/CQ
X/CQ
↑
0
T
0
1
X
X
Read
Loads new address
***
Q1/CQ
↑
X
X
1
X
X
Read
Read Continue
Increments address by 1
Q1/CQ
Q2/CQ
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