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參數(shù)資料
| 型號： | CXK79M72C164GB |
| 英文描述： | MEMORY-SigmaRAM 16Meg 1x1z HSTL I/O (256K x 72) (27 pages 368K Rev. 7/6/01) |
| 中文描述： | 內(nèi)存SigmaRAM 16Meg 1x1z HSTL的I / O（256 × 72）（27頁368K牧師7/6/01） |
| 文件頁數(shù)： | 23/30頁 |
| 文件大小： | 554K |
| 代理商： | CXK79M72C164GB |
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SONY
Σ
RAM CXK79M72C160GB / CXK79M36C160GB / CXK79M18C160GB
Preliminary
18Mb 1x1Lp, HSTL, rev 1.0
23 / 30
July 19, 2002
Bypass Register (DR - 1 bit)
The Bypass Register is one bit wide, and provides the minimum length serial path between TDI and TDO. It is loaded with
a logic “0” when the BYPASS instruction has been loaded in the Instruction Register and the TAP Controller is in the “Cap-
ture-DR” state. It is inserted between TDI and TDO when the BYPASS instruction has been loaded into the Instruction Reg-
ister and the TAP Controller is in the “Shift-DR” state.
ID Register (DR - 32 bits)
The ID Register is loaded with a predetermined device- and manufacturer-specific identification code when the IDCODE
instruction has been loaded into the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted
between TDI and TDO when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller
is in the “Shift-DR” state.
The ID Register is 32 bits wide, and is encoded as follows:
Bit 0 is the LSB of the ID Register, and Bit 31 is the MSB. When the ID Register is selected, TDI serially shifts data into the
MSB, and the LSB serially shifts data out through TDO.
Boundary Scan Register (DR - 123 bits for x72, 84 bits for x36, 65 bits for x18)
The Boundary Scan Register is equal in length to the number of active signal connections to the SRAM (excluding the TAP
pins) plus a number of place holder locations reserved for functional and/or density upgrades. It is loaded with the individual
logic states of all signals composing the SRAM’s I/O ring when the EXTEST-A, SAMPLE, or SAMPLE-Z instruction has
been loaded into the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted between TDI and
TDO when the EXTEST-A, SAMPLE, or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP
Controller is in the “Shift-DR” state.
The Boundary Scan Register contains the following bits:
Note
: CK and CK are connected to a differential input receiver that generates a single-ended input clock to these devices.
Therefore, in order to capture deterministic values for these signals in the Boundary Scan Register, they must be at opposite
logic levels when sampled.
Note
: When an external resistor RQ is connected between the ZQ pin and V
SS
, the value of the ZQ signal captured in the
Boundary Scan Register is non-deterministic.
Device
Revision Number
(31:28)
Part Number
(27:12)
Sony ID
(11:1)
Start Bit
(0)
256Kb x 72
xxxx
0000 0000 0101 0101
0000 1110 001
1
512Kb x 36
xxxx
0000 0000 0101 1001
0000 1110 001
1
1Mb x 18
xxxx
0000 0000 0101 1111
0000 1110 001
1
256Kb x 72
512Kb x 36
1Mb x 18
DQx
72
DQx
36
DQx
18
A, A1, A0
18
A, A1, A0
19
A, A1, A0
20
CK, CK
2
CK, CK
2
CK, CK
2
CQ1, CQ2, CQ1, CQ2
4
CQ1, CQ2, CQ1, CQ2
4
CQ1, CQ2, CQ1, CQ2
4
E1, ADV, W, Bx
11
E1, ADV, W, Bx
7
E1, ADV, W, Bx
5
E2, E3, EP2, EP3
4
E2, E3, EP2, EP3
4
E2, E3, EP2, EP3
4
ZQ
1
ZQ
1
ZQ
1
Place Holder
11
Place Holder
11
Place Holder
11
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