參數(shù)資料
型號: CXD2932AR-2
英文描述: GPS Base Band LSI
中文描述: 全球定位系統(tǒng)基帶芯片
文件頁數(shù): 17/27頁
文件大?。?/td> 264K
代理商: CXD2932AR-2
17
CXD2931R-9/GA-9
External Data Access Timing (XCS0, DCS0 to DCS5/no data wait)
(1) Read (byte access/no data wait)
(2) Write (byte access/no data wait)
No.
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
(i)
(j)
(k)
(l)
Item
Read/write cycle time (Fex: @20MHz)
Address delay time
Chip select fall delay time
Chip select rise delay time
Read signal fall delay time
Read signal rise delay time
Read data setup time
Read data hold time
Write signal fall delay time
Write signal rise delay time
Write data established time
Write data hold time
Min.
3
3
2
2
16
0
0
0
5
Typ.
100
Max.
12
13
13
8
10
2
3
12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
The load capacitance = 30pF.
CLKOUT
(h)
(b)
(c)
(d)
(e)
(f)
(g)
DADR
XCS0, DCS0 to DCS5
DRD
DB
(a)
(8)
CLKOUT
(l)
(b)
(c)
(d)
(i)
(j)
(k)
DADR
XCS0, DCS0 to DCS5
DWR
DB
(a)
(8)
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