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參數(shù)資料
| 型號(hào)： | CS96100-CM |
| 英文描述： | Consumer IC |
| 中文描述： | 消費(fèi)性IC |
| 文件頁數(shù)： | 17/58頁 |
| 文件大?。?/td> | 1099K |
| 代理商： | CS96100-CM |
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CS98100
17
2. TYPICAL APPLICATION
Figure 12
shows an example of a complete high-end DVD solution using the CS98100.
2.1
CS98100 Device Summary
RISC-32
Powerful 32-bit RISC processor
Optimizing C compiler and source level debug-
ger
Big or little endian data formats supported
MAC multiply/accumulate in two cycles with
C support.
2 Kbyte instruction cache, 2 Kbyte data cache.
Single cycle instructions run at 90 MHz.
DSP-32
Powerful 24/32-bit DSP processor
24-bit fixed point logic, with 54-bit accumula-
tor.
Single-cycle throughput, 2-cycle latency multi-
ply accumulate, 32-bit simple integer logic.
8 Kbyte instruction cache, 12 Kbyte program
visible local memory
Single cycle instructions run at 90 MHz.
SYSTEM CONTROLS
Include several hardware lockable semaphore
registers
General-purpose registers for inter-processor
communication
32-bit timers for I/O and other uses, with pro-
grammable interval rates
Both hardware and software interrupts on data
or debug
Performance monitors which measures DRAM
bandwidth, usage, and RSK performance
Built in PLLs generate all required clocks from
27 MHz input clock.
Memory Controller
Supports SDRAM, and SGRAM, from 2
MBytes to 32 MBytes.
Supports multiple banks of FLASH and ROM
up to 32 MBytes.
32-bit data bus for DRAM, 8 or 16-bit data bus
for ROM.
DATA FLOW ENGINE
Two DMA controllers – local memory based
and direct memory-to-memory
2432 bytes of internal memory, DMA to/from
main RAM into local SRAM.
Supports endian conversion and byte, short,
Figure 12. CS98100 Application
CS98100
ROM/
FLASH
1/
2
-1MB
SDRAM
4-8MB
Composite Video
IR
S-Video
Audio-
Up to 8 Channels
(4)Audio
DACs
Power
Reg.
Power
Switch
S/PDIF
Audio
ADC
Front Panel
Audio
DVD Loader
(IO Channel,
ATPAI or
Serial)
27M XTAL
Component Video
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