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參數(shù)資料
| 型號(hào)： | CS8406-CZZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 15/28頁 |
| 文件大小： | 0K |
| 描述： | IC XMITTER DGTL 192KHZ 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 類型： | 數(shù)字音頻接口發(fā)射器 |
| 應(yīng)用： | 車載音頻 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 759 (CN2011-ZH PDF) |
| 配用： | 598-1017-ND - BOARD EVAL FOR CS8416 RCVR |
| 其它名稱： | 598-1121-5 |
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22
DS580F6
CS8406
8.7
Interrupt 1 Status (07h) (Read Only)
For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once since
the register was last read. A ‘0’ me ans the associated interrupt condition has NOT occurred since the last
reading of the register. Reading the register resets all bits to ‘0’, unless the Interrupt Mode is set to level and
the interrupt source is still true. Status bits that are masked off in the associated mask register will always
be ‘0’ in this register. This register defaults to 00h.
TSLIP - AES3 transmitter source data slip interrupt
In data flows where OMCK, which clocks the AES3 transmitter, is asynchronous to the data source, this bit
will go high every time a data sample is dropped or repeated. When TCBL is an input, this bit will go high
on receipt of a new TCBL signal.
EFTC - E to F C-buffer transfer interrupt. The source for this bit is true during the E to F buffer transfer in
the C bit buffer management process.
8.8
Interrupt 2 Status (08h) (Read Only)
For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once since
the register was last read. A ‘0’ me ans the associated interrupt condition has NOT occurred since the last
reading of the register. Reading the register resets all bits to ‘0’, unless the Interrupt Mode is set to level and
the interrupt source is still true. Status bits that are masked off in the associated mask register will always
be ‘0’ in this register. This register defaults to 00h.
EFTU - E to F U-buffer transfer interrupt. (Block Mode only) The source of this bit is true during the E to F
buffer transfer in the U bit buffer management process.
8.9
Interrupt 1 Mask (09h)
The bits of this register serve as a mask for the Interrupt 1 register. If a mask bit is set to 1, the error is un-
masked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0,
the error is mas ked, meaning that its occurrence will not affect the INT pin or the status register. The bit
positions align with the corresponding bits in Interrupt 1 register. This register defaults to 00h.
7
6
5
432
1
0
TSLIP
0
EFTC
0
7
6
5
432
1
0
00
0
EFTU
0
7
6
5
432
1
0
TSLIPM
0
EFTCM
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS8406-CZZR | 功能描述:音頻發(fā)送器、接收器、收發(fā)器 IC 192 kHz Digital Audio Transmitter RoHS:否 制造商:Cirrus Logic 工作電源電壓:3.3 V, 5 V 電源電流:11.8 mA 通道數(shù)量:1 最大工作溫度:+ 70 C 接口類型:I2C, SPI 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSSOP-28 封裝: |
| CS8406-DNZ | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:192 kHz Digital Audio Interface Transmitter |
| CS8406-DNZR | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:192 kHz Digital Audio Interface Transmitter |
| CS8406-DS | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:192 KHZ DIGITAL AUDIO INTERFACE TRANSMITTER |
| CS8406-DSZ | 功能描述:音頻發(fā)送器、接收器、收發(fā)器 192kHz Digital Audio Transmitter RoHS:否 制造商:Cirrus Logic 工作電源電壓:3.3 V, 5 V 電源電流:11.8 mA 通道數(shù)量:1 最大工作溫度:+ 70 C 接口類型:I2C, SPI 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSSOP-28 封裝: |
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