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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | CS82C55A-5 |
| 寤犲晢锛� | Intersil |
| 鏂囦欢闋佹暩(sh霉)锛� | 23/29闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC I/O EXPANDER 24B 44PLCC |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 520 |
| 鎺ュ彛锛� | 鍙法绋� |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 24 |
| 涓柗杓稿嚭锛� | 鐒� |
| 闆绘簮闆诲锛� | 4.5 V ~ 5.5 V |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 44-LCC锛圝 褰㈠紩绶氾級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 44-PLCC |
| 鍖呰锛� | 绠′欢 |
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3
FN2969.10
November 16, 2006
Functional Diagram
Pin Description
SYMBOL
TYPE
DESCRIPTION
VCC
VCC: The +5V power supply pin. A 0.1渭F capacitor between VCC and GND is recommended for decoupling.
GND
GROUND
D0-D7
I/O
DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus.
RESET
I
RESET: A high on this input clears the control register and all ports (A, B, C) are set to the input mode with the 鈥淏us
Hold鈥� circuitry turned on.
CS
I
CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the Data Bus for CPU
communications.
RD
I
READ: Read is an active low input control signal used by the CPU to read status information or data via the data bus.
WR
I
WRITE: Write is an active low input control signal used by the CPU to load control words and data into the 82C55A.
A0-A1
I
ADDRESS: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three
ports or the control word register. A0 and A1 are normally connected to the least significant bits of the Address Bus
A0, A1.
PA0-PA7
I/O
PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are present on this port.
PB0-PB7
I/O
PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port.
PC0-PC7
I/O
PORT C: 8-bit input and output port. Bus hold circuitry is present on this port.
GROUP A
PORT A
(8)
GROUP A
PORT C
UPPER
(4)
GROUP B
PORT C
LOWER
(4)
GROUP B
PORT B
(8)
GROUP B
CONTROL
GROUP A
CONTROL
DATA BUS
BUFFER
READ
WRITE
CONTROL
LOGIC
RD
WR
A1
A0
RESET
CS
D7-D0
POWER
SUPPLIES
+5V
GND
BIDIRECTIONAL
DATA BUS
I/O
PA7-PA0
I/O
PC7-PC4
I/O
PC3-PC0
I/O
PB7-PB0
8-BIT
INTERNAL
DATA BUS
82C55A
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| ATMEGA8535L-8AUR | MCU AVR 8K FLASH 8MHZ 44TQFP |
| CP82C55A-5 | IC I/O EXPANDER 24B 40DIP |
| ATMEGA8535-16MUR | MCU AVR 8K FLASH 16MHZ 44QFN |
| CMQ82C55AZ96 | IC I/O EXPANDER 24B 44MQFP |
| CMQ82C55AZ | IC I/O EXPANDER 24B 44MQFP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| CS82C55A-596 | 鍔熻兘鎻忚堪:澶栧湇椹�(q奴)鍕曞櫒鑸囧師浠� - PCI PERIPH PRG-I/O 5V 5MHZ 44PLCC COMEL RoHS:鍚� 鍒堕€犲晢:PLX Technology 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FCBGA-1156 灏佽:Tray |
| CS82C55A-596S2497 | 鍒堕€犲晢:Harris Corporation 鍔熻兘鎻忚堪: |
| CS82C55A-5Z | 鍔熻兘鎻忚堪:澶栧湇椹�(q奴)鍕曞櫒鑸囧師浠� - PCI W/ANNEAL PERIPH PRG- I/O 5V 5MHZ 44PLCC RoHS:鍚� 鍒堕€犲晢:PLX Technology 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FCBGA-1156 灏佽:Tray |
| CS82C55A-5Z96 | 鍔熻兘鎻忚堪:澶栧湇椹�(q奴)鍕曞櫒鑸囧師浠� - PCI W/ANNEAL PERIPH PRG- I/O 5V 5MHZ 44PLCC RoHS:鍚� 鍒堕€犲晢:PLX Technology 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FCBGA-1156 灏佽:Tray |
| CS82C55A96 | 鍔熻兘鎻忚堪:澶栧湇椹�(q奴)鍕曞櫒鑸囧師浠� - PCI PERIPH PRG-I/O 5V 8MHZ 44PLCC COMEL RoHS:鍚� 鍒堕€犲晢:PLX Technology 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FCBGA-1156 灏佽:Tray |
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