- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗3768 > CS82C55A-5 (Intersil)IC I/O EXPANDER 24B 44PLCC PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | CS82C55A-5 |
| 寤犲晢锛� | Intersil |
| 鏂囦欢闋佹暩(sh霉)锛� | 11/29闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC I/O EXPANDER 24B 44PLCC |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 520 |
| 鎺ュ彛锛� | 鍙法绋� |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 24 |
| 涓柗杓稿嚭锛� | 鐒� |
| 闆绘簮闆诲锛� | 4.5 V ~ 5.5 V |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 44-LCC锛圝 褰㈠紩绶氾級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 44-PLCC |
| 鍖呰锛� | 绠′欢 |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�鐣�(d膩ng)鍓嶇11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�
19
FN2969.10
November 16, 2006
AC Electrical Specifications
VCC = +5V卤 10%, GND = 0V; TA = Operating Temperature Range
SYMBOL
PARAMETER
82C55A-5
82C55A
UNITS
TEST
CONDITIONS
MIN
MAX
MIN
MAX
READ TIMING
(1) tAR
Address Stable Before RD
0-0-
ns
(2) tRA
Address Stable After RD
0-0-
ns
(3) tRR
RD Pulse Width
250
-
150
-
ns
(4) tRD
Data Valid From RD
-
200
-
120
ns
1
(5) tDF
Data Float After RD
10
75
10
75
ns
2
(6) tRV
Time Between RDs and/or WRs
300
-
300
-
ns
WRITE TIMING
(7) tAW
Address Stable Before WR
0-0-
ns
(8) tWA
Address Stable After WR
20
-
20
-
ns
(9) tWW
WR Pulse Width
100
-
100
-
ns
(10) tDW
Data Valid to WR High
100
-
100
-
ns
(11) tWD
Data Valid After WR High
30
-
30
-
ns
OTHER TIMING
(12) tWB
WR = 1 to Output
-
350
-
350
ns
1
(13) tIR
Peripheral Data Before RD
0-0-
ns
(14) tHR
Peripheral Data After RD
0-0-
ns
(15) tAK
ACK Pulse Width
200
-
200
-
ns
(16) tST
STB Pulse Width
100
-
100
-
ns
(17) tPS
Peripheral Data Before STB High
20
-
20
-
ns
(18) tPH
Peripheral Data After STB High
50
-
50
-
ns
(19) tAD
ACK = 0 to Output
-
175
-
175
ns
1
(20) tKD
ACK = 1 to Output Float
20
250
20
250
ns
2
(21) tWOB
WR = 1 to OBF = 0
-
150
-
150
ns
1
(22) tAOB
ACK = 0 to OBF = 1
-
150
-
150
ns
1
(23) tSIB
STB = 0 to IBF = 1
-
150
-
150
ns
1
(24) tRIB
RD = 1 to IBF = 0
-
150
-
150
ns
1
(25) tRIT
RD = 0 to INTR = 0
-
200
-
200
ns
1
(26) tSIT
STB = 1 to INTR = 1
-
150
-
150
ns
1
(27) tAIT
ACK = 1 to INTR = 1
-
150
-
150
ns
1
(28) tWIT
WR = 0 to INTR = 0
-
200
-
200
ns
1
(29) tRES
Reset Pulse Width
500
-
500
-
ns
1, (Note)
NOTE: Period of initial Reset pulse after power-on must be at least 50
渭sec. Subsequent Reset pulses may be 500ns minimum.
82C55A
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| ATMEGA8535L-8AUR | MCU AVR 8K FLASH 8MHZ 44TQFP |
| CP82C55A-5 | IC I/O EXPANDER 24B 40DIP |
| ATMEGA8535-16MUR | MCU AVR 8K FLASH 16MHZ 44QFN |
| CMQ82C55AZ96 | IC I/O EXPANDER 24B 44MQFP |
| CMQ82C55AZ | IC I/O EXPANDER 24B 44MQFP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| CS82C55A-596 | 鍔熻兘鎻忚堪:澶栧湇椹�(q奴)鍕�(d貌ng)鍣ㄨ垏鍘熶欢 - PCI PERIPH PRG-I/O 5V 5MHZ 44PLCC COMEL RoHS:鍚� 鍒堕€犲晢:PLX Technology 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FCBGA-1156 灏佽:Tray |
| CS82C55A-596S2497 | 鍒堕€犲晢:Harris Corporation 鍔熻兘鎻忚堪: |
| CS82C55A-5Z | 鍔熻兘鎻忚堪:澶栧湇椹�(q奴)鍕�(d貌ng)鍣ㄨ垏鍘熶欢 - PCI W/ANNEAL PERIPH PRG- I/O 5V 5MHZ 44PLCC RoHS:鍚� 鍒堕€犲晢:PLX Technology 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FCBGA-1156 灏佽:Tray |
| CS82C55A-5Z96 | 鍔熻兘鎻忚堪:澶栧湇椹�(q奴)鍕�(d貌ng)鍣ㄨ垏鍘熶欢 - PCI W/ANNEAL PERIPH PRG- I/O 5V 5MHZ 44PLCC RoHS:鍚� 鍒堕€犲晢:PLX Technology 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FCBGA-1156 灏佽:Tray |
| CS82C55A96 | 鍔熻兘鎻忚堪:澶栧湇椹�(q奴)鍕�(d貌ng)鍣ㄨ垏鍘熶欢 - PCI PERIPH PRG-I/O 5V 8MHZ 44PLCC COMEL RoHS:鍚� 鍒堕€犲晢:PLX Technology 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FCBGA-1156 灏佽:Tray |
鐧�(f膩)甯冪穵鎬ラ噰璩�(g貌u)锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�
