j x 45
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� CS82C55A-5
寤犲晢锛� Intersil
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 20/29闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC I/O EXPANDER 24B 44PLCC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 520
鎺ュ彛锛� 鍙法绋�
杓稿叆/杓稿嚭鏁�(sh霉)锛� 24
涓柗杓稿嚭锛� 鐒�(w煤)
闆绘簮闆诲锛� 4.5 V ~ 5.5 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 44-LCC锛圝 褰㈠紩绶氾級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 44-PLCC
鍖呰锛� 绠′欢
27
FN2969.10
November 16, 2006
82C55A
Ceramic Leadless Chip Carrier Packages (CLCC)
D
j x 45o
D3
B
h x 45o
A
A1
E
L
L3
e
B3
L1
D2
D1
e1
E2
E1
L2
PLANE 2
PLANE 1
E3
B2
0.010
E H
S
0.010
E F
S
-E-
0.007
E F
M
S HS
B1
-H-
-F-
J44.A MIL-STD-1835 CQCC1-N44 (C-5)
44 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
0.064
0.120
1.63
3.05
6, 7
A1
0.054
0.088
1.37
2.24
-
B
0.033
0.039
0.84
0.99
4
B1
0.022
0.028
0.56
0.71
2, 4
B2
0.072 REF
1.83 REF
-
B3
0.006
0.022
0.15
0.56
-
D
0.640
0.662
16.26
16.81
-
D1
0.500 BSC
12.70 BSC
-
D2
0.250 BSC
6.35 BSC
-
D3
-
0.662
-
16.81
2
E
0.640
0.662
16.26
16.81
-
E1
0.500 BSC
12.70 BSC
-
E2
0.250 BSC
6.35 BSC
-
E3
-
0.662
-
16.81
2
e
0.050 BSC
1.27 BSC
-
e1
0.015
-
0.38
-
2
h
0.040 REF
1.02 REF
5
j
0.020 REF
0.51 REF
5
L
0.045
0.055
1.14
1.40
-
L1
0.045
0.055
1.14
1.40
-
L2
0.075
0.095
1.90
2.41
-
L3
0.003
0.015
0.08
0.38
-
ND
11
3
NE
11
3
N44
44
3
Rev. 0 5/18/94
NOTES:
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
3. Symbol 鈥淣鈥� is the maximum number of terminals. Symbols 鈥淣D鈥�
and 鈥淣E鈥� are the number of terminals along the sides of length
鈥淒鈥� and 鈥淓鈥�, respectively.
4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer鈥檚 option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Dimension 鈥淎鈥� controls the overall package thickness. The maxi-
mum 鈥淎鈥� dimension is package height before being solder dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
鐩搁棞(gu膩n)PDF璩囨枡
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
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