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參數(shù)資料
| 型號： | CS5422GDWFR24 |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 116K |
| 代理商： | CS5422GDWFR24 |
CS5421
http://onsemi.com
4
ELECTRICAL CHARACTERISTICS (continued)
(0
°
C < T
A
< 70
°
C; 0
°
C < T
J
< 125
°
C; R
OSC
= 30.9 k, C
COMP1,2
= 0.1
μ
F,
10.8
V < V
CC
< 13.2
V;
C
GATE(H)1,2
=
C
GATE(L)1,2
= 1.0
nF, unless otherwise specified.)
Characteristic
Unit
Max
Typ
Min
Test Conditions
PWM Comparator
Transient Response
COMP1,2 = 1.0 V, V
FB1(2)
= V
FFB1(2)
= 0 to 1.2 V
–
150
300
ns
PWM Comparator Offset
V
FFB1(2)
= 0 V; Increase COMP1,2 until
GATE(H)1,2 starts switching
0.30
0.45
0.60
V
Artificial Ramp
Duty cycle = 50%, Note 3.
40
70
100
mV
V
FFB1(2)
Bias Current
V
FFB1(2)
= 0 V
–
0.4
1.5
μ
A
V
FFB1(2)
Input Range
–
0.0
–
1.1
V
Minimum Pulse Width
–
–
–
300
ns
Oscillator
Switching Frequency
R
OSC
= 61.9 k; Measure GATE(H)2, Note 3.
112
150
188
kHz
Switching Frequency
R
OSC
= 30.9 k; Measure GATE(H)2
224
300
376
kHz
Switching Frequency
R
OSC
= 11.8 k; Measure GATE(H)2, Note 3.
600
750
900
kHz
R
OSC
Voltage
R
OSC
= 30.9 k, Note 3.
0.970
1.000
1.030
V
Phase Difference
–
–
180
–
°
Supply Currents
V
CC
Current
COMP1,2 = 0 V (No Switching)
–
16
22
mA
SGND Current
–
75
150
225
μ
A
Undervoltage Lockout
Start Threshold
GATE(H) Switching; COMP1,2 charging
7.8
8.6
9.6
V
Stop Threshold
GATE(H) not switching; COMP1,2 discharging
7.0
7.8
8.6
V
Hysteresis
Start–Stop
0.5
0.8
1.5
V
3. Guaranteed by design, not 100% tested in production.
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
16 Lead SO Narrow
PIN SYMBOL
FUNCTION
1
GATE(H)1
High Side Switch FET driver pin for the channel 1 FET.
2
GATE(L)1
Low Side Synchronous FET driver pin for the channel 1 FET.
3
PGND1
High Current ground for the GATE(H)1 and GATE(L)1 pins.
4
LGND
Logic ground. All control circuits are referenced to this pin. IC
substrate connection.
5
SGND
Ground sense for the internal reference.
6
V
FFB1
Input for the channel 1 PWM comparator.
7
V
FB1
Error amplifier inverting input for channel 1.
8
COMP1
Channel 1 Error Amp output. PWM Comparator reference
input. A capacitor to LGND provides Error Amp compensa-
tion. The same capacitor provides Soft Start timing for chan-
nel 1. This pin also disables the channel 1 output when
pulled below 0.3 V.
9
COMP2
Channel 2 Error Amp output. PWM Comparator reference
input. A capacitor to LGND provides Error Amp compensa-
tion and Soft Start timing for channel 2. Channel 2 output is
disabled when this pin is pulled below 0.3 V.
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