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參數(shù)資料
| 型號： | CS5422GDWFR24 |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 116K |
| 代理商： | CS5422GDWFR24 |
CS5421
http://onsemi.com
11
The upper MOSFET switching losses are caused during
MOSFET switch–on and switch–off and can be determined
by using the following formula:
PSWH
PSWH(ON)
VIN
IOUT
PSWH(OFF)
(tRISE
6.0T
tFALL)
where:
P
SWH(ON)
= upper MOSFET switch–on losses;
P
SWH(OFF)
= upper MOSFET switch–off losses;
V
IN
= input voltage;
I
OUT
= load current;
t
RISE
= MOSFET rise time (from FET manufacturer’s
switching characteristics performance curve);
t
FALL
= MOSFET fall time (from FET manufacturer’s
switching characteristics performance curve);
T = 1/f
SW
= period.
The total power dissipation in the switching MOSFET can
then be calculated as:
PHFET(TOTAL)
PRMS(H)
PSWH(ON)
PSWH(OFF)
where:
P
HFET(TOTAL)
= total switching (upper) MOSFET losses;
P
RMS(H)
= upper MOSFET switch conduction Losses;
P
SWH(ON)
= upper MOSFET switch–on losses;
P
SWH(OFF)
= upper MOSFET switch–off losses;
Once the total power dissipation in the switching FET is
known, the maximum FET switch junction temperature can
be calculated:
TJ
TA
[PHFET(TOTAL)
R JA]
where:
T
J
= FET junction temperature;
T
A
= ambient temperature;
P
HFET(TOTAL)
= total switching (upper) FET losses;
R
Θ
JA
= upper FET junction–to–ambient thermal resistance.
Selection of the Synchronous (Lower) FET
The switch conduction losses for the lower FET can be
calculated as follows:
IRMS2
RDS(ON)
[IOUT
(1.0
D)]2
RDS(ON)
PRMS(L)
where:
P
RMS(L)
= lower MOSFET conduction losses;
I
OUT
= load current;
D = Duty Cycle;
R
DS(ON)
= lower FET drain–to–source on–resistance.
The synchronous MOSFET has no switching losses,
except for losses in the internal body diode, because it turns
on into near zero voltage conditions. The MOSFET body
diode will conduct during the non–overlap time and the
resulting power dissipation (neglecting reverse recovery
losses) can be calculated as follows:
PSWL
VSD
ILOAD
non–overlap time
fSW
where:
P
SWL
= lower FET switching losses;
V
SD
= lower FET source–to–drain voltage;
I
LOAD
= load current;
Non–overlap
time
GATE(H)–to–GATE(L) delay (from CS5421 data sheet
Electrical Characteristics section);
f
SW
= switching frequency.
The total power dissipation in the synchronous (lower)
MOSFET can then be calculated as:
PLFET(TOTAL)
=
GATE(L)–to–GATE(H)
or
PRMS(L)
PSWL
where:
P
LFET(TOTAL)
= Synchronous (lower) FET total losses;
P
RMS(L)
= Switch Conduction Losses;
P
SWL
= Switching losses.
Once the total power dissipation in the synchronous FET
is known the maximum FET switch junction temperature
can be calculated:
TJ
TA
[PLFET(TOTAL)
R JA]
where:
T
J
= MOSFET junction temperature;
T
A
= ambient temperature;
P
LFET(TOTAL)
= total synchronous (lower) FET losses;
R
Θ
JA
= lower FET junction–to–ambient thermal resistance.
Control IC Power Dissipation
The power dissipation of the IC varies with the MOSFETs
used, V
CC
, and the CS5421 operating frequency. The
average MOSFET gate charge current typically dominates
the control IC power dissipation.
The IC power dissipation is determined by the formula:
PCONTROL(IC)
ICC1VCC1
PGATE(L)1
PGATE(H)2
PGATE(L)2
PGATE(H)1
where:
P
CONTROL(IC)
= control IC power dissipation;
I
CC1
= IC quiescent supply current;
V
CC1
= IC supply voltage;
P
GATE(H)
= upper MOSFET gate driver (IC) losses;
P
GATE(L)
= lower MOSFET gate driver (IC) losses.
The upper (switching) MOSFET gate driver (IC) losses
are:
PGATE(H)
QGATE(H)
fSW
VCC
where:
P
GATE(H)
= upper MOSFET gate driver (IC) losses;
Q
GATE(H)
= total upper MOSFET gate charge at V
CC
;
f
SW
= switching frequency;
The lower (synchronous) MOSFET gate driver (IC)
losses are:
PGATE(L)
QGATE(L)
fSW
VGATE(L)
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