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參數(shù)資料
| 型號： | CS5422GDWFR24 |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 116K |
| 代理商： | CS5422GDWFR24 |
CS5421
http://onsemi.com
3
ABSOLUTE MAXIMUM RATINGS (continued)
Pin Symbol
I
SINK
I
SOURCE
V
MIN
V
MAX
Pin Name
R
OSC
Oscillator Resistor
4.0 V
–0.3 V
1.0 mA
1.0 mA
GATE(H)1
,
GATE(H)2
High–Side FET Driver
for Channel 1 or 2
16 V
–0.3 V
1.5 A peak
200 mA DC
1.5 A peak
200 mA DC
GATE(L)1
,
GATE(L)2
Low–Side FET Driver for
Channel 1 or 2
16 V
–0.3 V
1.5 A peak
200 mA DC
1.5 A peak
200 mA DC
PGND1
Power Ground for Channel 1
0 V
0 V
1.5 A peak
200 mA DC
N/A
PGND2
Power Ground for Channel 2
0 V
0 V
1.5 A peak
200 mA DC
N/A
SGND
Ground for Internal Reference
150 mV
0 V
1.0 mA
N/A
LGND
Logic Ground
0 V
0 V
50 mA
N/A
ELECTRICAL CHARACTERISTICS
(0
°
C < T
A
< 70
°
C; 0
°
C < T
J
< 125
°
C; R
OSC
= 30.9 k, C
COMP1,2
= 0.1
μ
F,
10.8
V < V
CC
< 13.2
V;
C
GATE(H)1,2
=
C
GATE(L)1,2
= 1.0
nF, unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Error Amplifier
V
FB1(2)
Bias Current
V
FB1(2)
= 0 V
–
0.1
1.0
μ
A
COMP1,2 Source Current
COMP1,2 = 1.2 V to 2.5 V; V
FB1(2)
= 0.8 V
15
30
60
μ
COMP1,2 Sink Current
COMP1,2 = 1.2 V; V
FB1(2)
= 1.2 V
15
30
60
μ
A
Reference Voltage 1
COMP1 = V
FB1
; 25
°
C < T
J
< 125
°
C
0.992
1.000
1.008
V
Reference Voltage 2
COMP2 = V
FB2
0.980
1.000
1.020
V
COMP1,2 Max Voltage
V
FB1(2)
= 0.8 V
3.0
3.3
–
V
COMP1,2 Min Voltage
V
FB1(2)
= 1.2 V
–
0.25
0.35
V
Open Loop Gain
–
–
95
–
dB
Unity Gain Band Width
–
–
40
–
kHz
PSRR @ 1.0 kHz
–
–
70
–
dB
Transconductance
–
–
32
–
mmho
Output Impedance
–
–
2.5
–
M
GATE(H) and GATE(L)
High Voltage (AC)
Measure: V
CC
– GATE(L)1,2;
V
CC
– GATE(H)1,2; Note 2.
–
0
0.5
V
Low Voltage (AC)
Measure:GATE(L)1,2 or GATE(H)1,2; Note 2.
–
0
0.5
V
Rise Time
1.5 V < GATE(L)1,2 < V
CC
– 1.5 V
1.5 V < GATE(H)1,2 < V
CC
– 1.5 V
–
25
60
ns
Fall Time
V
CC
– 1.5 > GATE(L)1,2 > 1.5 V
V
CC
– 1.5 > GATE(H)1,2 > 1.5 V
–
20
60
ns
GATE(H) to GATE(L) Delay
GATE(H)1,2 < 1.0 V, GATE(L)1,2 > 1.0 V
40
70
100
ns
GATE(L) to GATE(H) Delay
GATE(L)1,2 < 1.0 V, GATE(H)1,2 > 1.0 V
40
70
100
ns
GATE(H)1(2) and GATE(L)1(2)
pull–down
Resistance to PGND
Note 2.
50
125
280
k
2. Guaranteed by design, not 100% tested in production.
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