參數(shù)資料
型號(hào): CS5346-DQZR
廠商: CIRRUS LOGIC INC
元件分類: ADC
中文描述: 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQFP48
封裝: LEAD FREE, MS-022, LQFP-48
文件頁數(shù): 10/40頁
文件大?。?/td> 402K
代理商: CS5346-DQZR
18
DS861PP2
CS5346
SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT
Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL =30pF.
17. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
kHz
RST Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
s
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
s
Clock Low time
tlow
4.7
-
s
Clock High Time
thigh
4.0
-
s
Setup Time for Repeated Start Condition
tsust
4.7
-
s
SDA Hold Time from SCL Falling
thdd
0-
s
SDA Setup time to SCL Rising
tsud
250
-
ns
Rise Time of SCL and SDA
trc, trd
-1
s
Fall Time SCL and SDA
tfc, tfd
-
300
ns
Setup Time for Stop Condition
tsusp
4.7
-
s
Acknowledge Delay from SCL Falling
tack
300
1000
ns
t buf
t hdst
t
low
t r
t f
t
hdd
t high
t sud
t sust
t susp
Stop
Start
Stop
Repeated
SDA
SCL
t irs
RST
Figure 5. Control Port Timing - IC Format
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