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參數(shù)資料
| 型號(hào)： | CS517GDR16 |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大小： | 176K |
| 代理商： | CS517GDR16 |
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Applications Information: continued
C
12
A heatsink may be added to TO-220 components to reduce
their thermal impedance. A number of PC board layout
techniques such as thermal bias and additional copper foil
area can be used to improve the power handling capability
of surface mount components.
EMI Management
As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing for
compliance with EMI/ EMC regulations, additional compo-
nents may be added to reduce noise emissions. These com-
ponents are not required for regulator operation and exper-
imental results may allow them to be eliminated. The input
filter inductor may not be required because bulk filter and
bypass capacitors, as well as other loads located on the
board will tend to reduce regulator di/ dt effects on the cir-
cuit board and input power supply. Placement of the
power component to minimize routing distance will also
help to reduce emissions.
Figure 18: Filter components
Figure 19: Input Filter
Layout Guidelines
1. Place 12V filter capacitor next to the IC and connect
capacitor ground to pin 11 (PGnd).
2. Connect pin 11 (PGnd) with a separate trace to the
ground terminals of the 5V input capacitors.
3. Place fast feedback filter capacitor next to pin 8 (V
FFB
)
and connect it’s ground terminal with a separate, wide
trace directly to pin 14 (LGnd).
4. Connect the ground terminals of the Compensation
capacitor directly to the ground of the fast feedback filter
capacitor to prevent common mode noise from effecting
the PWM comparator.
5. Place the output filter capacitor(s) as close to the load as
possible and connect the ground terminal to pin 14 (LGnd).
6. Connect the V
FB
pin directly to the load with a separate
trace (remote sense).
7. Place 5V input capacitors close to the switching MOSFET
and synchronous MOSFET.
Route gate drive signals V
GATE(H)
(pin 10) and V
GATE(L)
(pin 12 when used) with traces that are a minimum of 0.025
inches wide.
Figure 20: Layout Guidelines
15
To the negative terminal of the
input capacitors
11
100pF
V
FFB
8
OFF TIME
5
SOFTSTART
V
CC
0.1
μ
F
To the negative terminal of the output capacitors
1.0
μ
F
V
COMP
+
2
μ
H
1200
μ
F x 3/16V
33
1000pF
2
μ
H
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