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參數(shù)資料
| 型號： | CS51313GDR16 |
| 廠商： | ZF Electronics Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Micropower 5V, 100mA Low Dropout Linear Regulator |
| 中文描述： | 微5V的，100mA的低壓差線性穩(wěn)壓器 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大小： | 248K |
| 代理商： | CS51313GDR16 |
2
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
Absolute Maximum Ratings
Pin Symbol
Pin Name
V
MAX
V
MIN
I
SOURCE
I
SINK
V
REF
V
CC
Bandgap Reference Voltage
IC Power Input
6V
16V
-0.3V
-0.3V
1mA
N/A
1mA
1.5A Peak
200mA DC
5mA
1mA
COMP
V
FB
, V
OUT
, V
ID0-4
Compensation Pin
Voltage Feedback Input, Output
Voltage Sense Pin, Voltage
ID DAC Inputs
Off-Time Pin
High-Side, Low Side FET Drivers
6V
6V
-0.3V
-0.3V
1mA
1mA
C
OFF
GATE(H), GATE(L)
6V
16V
-0.3V
-0.3V
1mA
1.5APeak
200mA DC
1mA
30mA
1.5A Peak
200mA DC
50mA
1.5A Peak
200mA DC
30mA
1mA
N/A
PWRGD
OVP
Gnd
Power-Good Output
Overvoltage Protection
Ground
6V
15V
0V
-0.3V
-0.3V
0V
C
1,2,3,4,6
V
IDO
– V
ID4
Voltage ID DAC inputs. These pins are internally pulled up to
5.65V if left open. V
ID4
selects the DAC range. When V
ID4
is
high (logic one), the Error Amp reference range is 2.125V to
3.525V with 100mV increments. When V
ID4
is low (logic zero),
the Error amp reference voltage is 1.325V to 2.075V with 50mV
increments.
Input power supply pin for the internal circuitry.
Decouple with filter capacitor to Gnd.
High side switch FET driver pin
Ground pin.
Low side synchronous FET driver pin.
Power-Good Output. Open collector output drives low when
V
FB
is out of regulation.
Error amp output. PWM comparator inverting input.
A capacitor to Gnd provides error amp compensation.
Off-Time Capacitor Pin. A capacitor from this pin to Gnd sets
the off time for the regulator
Current limit comparator inverting input.
Error amp inverting input, PWM comparator non-inverting
input, current limit comparator non-inverting input, PWRGD
and OVP comparator input.
Bandgap Reference Voltage. It can be used to generate other
regulated output voltages.
Overvoltage protection pin. Goes high when overvoltage
condition is detected on V
FB
.
9
V
CC
10
11
12
14
GATE(H)
Gnd
GATE(L)
PWRGD
16
COMP
15
C
OFF
8
7
V
OUT
V
FB
5
V
REF
13
OVP
Operating Junction Temperature, T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead Temperature Soldering
Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 sec. max above 183°C, 230°C peak
Storage Temperature Range, T
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65° to 150°C
ESD Susceptibility (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
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