參數資料
| 型號： | CS4955-CQZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數： | 7/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VID ENCODER NTSC/PAL 48-TQFP |
| 標準包裝： | 2,000 |
| 類型： | 視頻編碼器 |
| 電壓 - 電源，模擬： | 3.15 V ~ 5.25 V |
| 電壓 - 電源，數字： | 3.15 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
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CS4954 CS4955
DS278F6
15
4.12 Teletext Services
The CS4954/5 encodes the most common teletext
formats, such as European Teletext, World Stan-
dard Teletext (PAL and NTSC), and North Ameri-
can Teletext (NABTS).
Teletext data can be inserted in any of the TV lines
(blanking lines as well as active lines). In addition
the blanking lines can be individually allocated for
Teletext instantiation.
The input timing for teletext data is user program-
mable. See the section Teletext Services for further
details.
Teletext data can be independently inserted on ei-
ther one or all of the CVBS_1, CVBS_2, or S-video
signals.
4.13 Wide-Screen Signaling Support and
CGMS
Insertion of wide-screen signal encoding for PAL
and NTSC standards is supported and CGMS
(Copy Generation Management System) for NTSC
in Japan. Wide-screen signals are inserted in lines
23 and 336 for PAL, and lines 20 and 283 for
NTSC.
4.14 VBI Encoding
This chip supports the transmission of control sig-
nals in the vertical blanking time interval according
to SMPTE RP 188 recommendations. VBI encoded
data can be independently inserted into any or all of
CVBS_1, CVBS_2 or S-video signals.
4.15 Control Registers
The control and configuration of the CS4954/5 is
accomplished primarily through the control regis-
ter block. All of the control registers are uniquely
addressable via the internal address register. The
control register bits are initialized during device
RESET.
See the Programming section of this data sheet for
the individual register bit allocations, bit operation-
al descriptions, and initialization states.
4.16 Testability
The digital circuits are completely scanned by an
internal scan chain, thus providing close to 100%
fault coverage.
5.
OPERATIONAL DESCRIPTION
5.1
Reset Hierarchy
The CS4954/5 is equipped with an active low asyn-
chronous reset input pin, RESET. RESET is used to
initialize the internal registers and the internal state
machines for subsequent default operation. See the
electrical and timing specification section of this
data sheet for specific CS4954/5 device RESET
and power-on signal timing requirements and re-
strictions.
While the RESET pin is held low, the host interface
in the CS4954/5 is disabled and will not respond to
host-initiated bus cycles. All outputs are valid after
a time period following RESET pin low.
A device RESET initializes the CS4954/5 internal
registers to their default values as described by Ta-
ble 9, Control Registers. In the default state, the
CS4954/5 video DACs are disabled and the device
is internally configured to provide blue field video
data to the DACs (any input data present on the
V [7:0] pins is ignored at this time). Otherwise, the
CS4954/5 registers are configured for NTSC-M
output and ITU R.BT601 output timing operation.
At a minimum, the DAC Registers (0x04 and 0x05)
must be written (to enable the DACs) and the
IN_MODE bit of the CONTROL_0 Register
(0x01) must be set (to enable ITU R.BT601 data in-
put on V [7:0]) for the CS4954/5 to become opera-
tional after RESET.
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