參數(shù)資料
型號(hào)： CS4955-CQZR
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 27/60頁(yè)
文件大?。?/td> 0K
描述： IC VID ENCODER NTSC/PAL 48-TQFP
標(biāo)準(zhǔn)包裝： 2,000
類型： 視頻編碼器
電壓 - 電源，模擬： 3.15 V ~ 5.25 V
電壓 - 電源，數(shù)字： 3.15 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 帶卷 (TR)
CS4954 CS4955
DS278F6
33
7.4.2 Chrominance DAC
The C output pin is driven from a 10-bit 27 MHz
current output DAC that internally receives the C
or chrominance portion of the video signal (color
only). The C DAC is designed to drive proper video
levels into a 37.5
Ω load. Reference the detailed
electrical section of this data sheet for the exact C
digital to analog AC and DC performance data. The
EN_C enable control register bit in Control Register
1 (0×05) is provided to enable or disable the
chrominance DAC. To completely disable or for
low power device operation, the chrominance DAC
can be totally shut down via the SVIDCHR_PD
register bit in Control Register 4 (0×04). In this
mode turn-on using the control register will not be
instantaneous.
7.4.3 CVBS DAC
The CVBS output pin is driven from a 10-bit
27 MHz current output DAC that internally re-
ceives a combined luma and chroma signal to pro-
vide composite video output. The CVBS DAC is
designed to drive proper composite video levels
into a 37.5
Ω load. Reference the detailed electrical
section of this data sheet for the exact CVBS digital
to analog AC and DC performance data. The
EN_COM enable control register bit, in Control
Register 1 (0×05), is provided to enable or disable
the output pin. When disabled, there is no current
flow from the output. To completely disable or for
low power device operation, the CVBS37 DAC can
be totally shut down via the COMDAC_PD control
register bit in Control Register 4 (0×04). In this
mode turn-on using the control register will not be
instantaneous.
7.4.4 Red DAC
The Red output pin is driven from a 10-bit 27 MHz
current output DAC that internally receives either
red component video data or V (Cr) data. The Red
DAC is designed to drive proper component video
levels into a 37.5
Ω load. Reference the detailed
electrical section of this data sheet for the exact red
digital to analog AC and DC performance data. The
EN_R enable control register bit in Control Regis-
ter 1 (0×05) is provided to enable or disable the out-
put pin. When disabled, there is no current flow
from the output. To complete disable or for low
power device operation, the red DAC can be totally
shut down via the R_PD control register bit in
Control Register 4 (0×04). In this mode turn-on
using the control register will not be instantaneous.
7.4.5 Green DAC
The Green output pin is driven from a 10-bit
27 MHz current output DAC that internally re-
ceives either Green component video data, Y lumi-
nance data or CVBS data depending upon its
configuration. See Table 1, “CVBS DAC” on
The Green DAC is designed to drive proper com-
posite video levels into a 37.5
Ω load. Reference
the detailed electrical section of this data sheet for
the exact green digital to analog AC and DC perfor-
mance data. The EN_G enable control register bit,
in Control Register 1 (0×05), is provided to enable
or disable the output pin. When disabled, there is
no current flow from the output. To completely dis-
able or for low power device operation, the green
DAC can be totally shut down via the G_PD con-
trol register bit in Control Register 4 (0×04). In this
mode turn-on using the control register will not be
instantaneous.
7.4.6 Blue DAC
The Blue output pin is driven from a 10-bit 27 MHz
current output DAC that internally receives either
blue component video data or U (Cb) data. The
Blue DAC is designed to drive proper component
video levels into a 37.5
Ω load. Reference the de-
tailed electrical section of this data sheet for the ex-
act blue digital to analog AC and DC performance
data. The EN_B enable control register bit, in Con-
trol Register 5 (0×05), is provided to enable or dis-
able the output pin. When disabled, there is no
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