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參數(shù)資料
| 型號： | CS4955-CQZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 6/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VID ENCODER NTSC/PAL 48-TQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 視頻編碼器 |
| 電壓 - 電源，模擬： | 3.15 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 3.15 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
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CS4954 CS4955
14
DS278F6
the six DACs has its own associated DAC enable
bit. In the Disable Mode, the 10-bit DACs source
(or sink) zero current.
When running the DACs with a low-impedance
load, a minimum of three DACs must be powered
down. When running the DACs with a high-imped-
ance load, all the DACs can be enabled simulta-
neously.
For lower power standby scenarios, the CS4954/5
also provides power shut-off control for the DACs.
Each DAC has an associated DAC shut-off bit.
4.8
Voltage Reference
The CS4954/5 is equipped with an on-board volt-
age reference generator (1.232 V) that is used by
the DACs. The internal reference voltage is accu-
rate enough to guarantee a maximum of 3% overall
gain error on the analog outputs. However, it is
possible to override the internal reference voltage
by applying an external voltage source to the VREF
pin.
4.9
Current Reference
The DAC output current-per-bit is derived in the
current reference block. The current step is speci-
fied by the size of resistor placed between the ISET
current reference pin and electrical ground.
A 4 k
Ω resistor needs to be connected between
ISET pin and GNDA. The DAC output currents are
optimized to drive either a doubly terminated 75 W
load (low impedence mode) or a double terminated
300
Ω load (high impedence mode). The 2 output
current modes are software selectable via a register
bit.
4.10 Host Interface
The CS4954/5 provides a parallel 8-bit data inter-
face for overall configuration and control. The host
interface uses active-low read and write strobes,
along with an active-low address enable signal, to
provide microprocessor-compatible read and write
cycles. Indirect host addressing to the CS4954/5 in-
ternal registers is accomplished via an internal ad-
dress register that is uniquely accessible via bus
write cycles for the device when the host address
enable signal is asserted.
The CS4954/5 also provides an IC-compatible se-
rial interface for device configuration and control.
This port can operate in standard (up to 100 kb/sec)
or fast (up to 400 kb/sec) modes. When in IC
mode, the parallel data interface pins, PDAT [7:0],
can be used as a general purpose I/O port controlled
by the IC interface.
4.11 Closed Caption Services
The CS4954/5 supports the generation of NTSC
Closed Caption services. Line 21 and Line 284 cap-
tioning can be generated and enabled independent-
ly via a set of control registers. When enabled,
clock run-in, start bit, and data bytes are automati-
cally inserted at the appropriate video lines. A con-
venient interrupt protocol simplifies the software
interface between the host processor and the
CS4954/5.
DAC
Pin #
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Y
48
Y
CVBS_2
C
47
CCC
-
CVBS
44
CVBS_1
R
39
R
Cr (V)
-
R
Cr (V)
G
40
G
Y
CVBS_2
G
Y
B43B
Cb (U)
-
B
Cb (U)
Table 1. DAC configuration Modes
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