參數(shù)資料
型號: CS4384-CQZ
廠商: Cirrus Logic Inc
文件頁數(shù): 29/52頁
文件大?。?/td> 0K
描述: IC DAC 8CH 103DB 192KHZ 48LQFP
標準包裝: 250
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 8
電壓電源: 模擬和數(shù)字
功率耗散(最大): 520mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應商設備封裝: 48-LQFP
包裝: 托盤
輸出數(shù)目和類型: 8 電壓,單極
采樣率(每秒): 216k
產(chǎn)品目錄頁面: 757 (CN2011-ZH PDF)
配用: 598-1525-ND - BOARD EVAL FOR CS4384 DAC
其它名稱: 598-1062
DS620F1
35
CS4384
6. REGISTER DESCRIPTION
Note:
All registers are read/write in IC Mode and write only in SPI, unless otherwise noted.
6.1
Chip Revision (Address 01h)
6.1.1
Part Number ID (PART) [Read Only]
00000- CS4384
6.1.2
Revision ID (REV) [Read Only]
000 - Revision A0
001 - Revision B0
Function:
This read-only register can be used to identify the model and revision number of the device.
6.2
Mode Control 1 (Address 02h)
6.2.1
Control Port Enable (CPEN)
Default = 0
0 - Disabled
1 - Enabled
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone Mode. The Control Port Mode can
be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the reg-
isters and the pin definitions will conform to Control Port Mode. To accomplish a clean power-up, the user
should write this bit within 10 ms following the release of Reset.
6.2.2
Freeze Controls (FREEZE)
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes taking effect until the
FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneously,
enable the FREEZE Bit, make all register changes, then Disable the FREEZE bit.
7
6
5
432
10
PART4
PART3
PART2
PART1
PART0
REV2
REV1
REV0
00
0
-
7
6
5
432
10
CPEN
FREEZE
DSD/PCM
DAC4_DIS
DAC3_DIS
DAC2_DIS
DAC1_DIS
PDN
0
000
01
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