參數(shù)資料
型號(hào)： CS4384-CQZ
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 20/52頁(yè)
文件大小： 0K
描述： IC DAC 8CH 103DB 192KHZ 48LQFP
標(biāo)準(zhǔn)包裝： 250
位數(shù)： 24
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 8
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 520mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP
包裝： 托盤
輸出數(shù)目和類型： 8 電壓，單極
采樣率（每秒）： 216k
產(chǎn)品目錄頁(yè)面： 757 (CN2011-ZH PDF)
配用： 598-1525-ND - BOARD EVAL FOR CS4384 DAC
其它名稱： 598-1062
DS620F1
27
CS4384
Figure 22. DSD Phase Modulation Mode Diagram
4.9
Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4384 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. The Typical Connection Diagram shows the rec-
ommended power arrangements, with VA, VD, VLC, and VLS connected to clean supplies. If the ground
planes are split between digital ground and analog ground, the GND pins of the CS4384 should be connect-
ed to the analog ground plane.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted
coupling into the DAC.
4.9.1
Capacitor Placement
Decoupling capacitors should be placed as close to the DAC as possible, with the low value ceramic ca-
pacitor being the closest. To further minimize impedance, these capacitors should be located on the same
layer as the DAC. If desired, all supply pins with similar voltage ratings may be connected to the same
supply, but a decoupling capacitor should still be placed on each supply pin.
Note:
All decoupling capacitors should be referenced to analog ground.
The CDB4384 evaluation board demonstrates the optimum layout and power supply arrangements.
4.10
Analog Output and Filtering
The CS4384 does not include phase or amplitude compensation for an external filter. Therefore, the DAC
system phase and amplitude response will be dependent on the external analog circuitry.
Figure 23 shows how the full-scale analog output level specification is derived.
Figure 24 shows how the recommended output filtering with location for optional mute circuit.
BCKA
(128Fs)
BCKD
(64Fs)
DSD_SCLK
DSDAx,
DSDBx
D1
D0
D2
D0
DSD_SCLK
DSDAx,
DSDBx
BCKA
(64Fs)
DSD_SCLK
DSD Phase
Modulation Mode
DSD Normal Mode
Not Used
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