I2C Read To read from the device, follow the procedure" />
參數(shù)資料
型號(hào): CS4341A-KSZ
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 5/34頁(yè)
文件大?。?/td> 0K
描述: IC DAC STER 24BIT 192KHZ 16SOIC
標(biāo)準(zhǔn)包裝: 48
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
功率耗散(最大): 90mW
工作溫度: -10°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 托盤(pán)
輸出數(shù)目和類(lèi)型: 2 電壓,單極
采樣率(每秒): 192k
產(chǎn)品目錄頁(yè)面: 756 (CN2011-ZH PDF)
其它名稱(chēng): 598-1633
CS4341A
DS582F2
13
3.9.3b
I2C Read
To read from the device, follow the procedure below while adhering to the control port
Switching Specifications.
1) Initiate a START condition to the I2C bus followed by the address byte. The upper 6 bits
must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must
be 1. The eighth bit of the address byte is the R/W bit.
2) After transmitting an acknowledge (ACK), the device will then transmit the contents of
the register pointed to by the MAP. The MAP register will contain the address of the last
register written to the MAP, or the default address (see section 3.9.2) if an I2C read is the
first operation performed on the device.
3) Once the device has transmitted the contents of the register pointed to by the MAP, issue
an ACK.
4) If the INCR bit is set to 1, the device will continue to transmit the contents of successive
registers. Continue providing a clock and issue an ACK after each byte until all the desired
registers are read, then initiate a STOP condition to the bus.
5) If the INCR bit is set to 0 and further I2C reads from other registers are desired, it is nec-
essary to initiate a repeated START condition and follow the procedure detailed from step
1. If no further reads from other registers are desired, initiate a STOP condition to the bus.
SD A
SC L
001000
AD 0
R/W
Sta rt
ACK
DATA
1-8
ACK
DA TA
1-8
ACK
Stop
NOT E
N O T E : If operation is a w rite, this byte contains the M em ory A ddress P ointer, M A P . If
operation is a read, this byte contains the data of the register pointed to by the M A P .
Figure 7. Control Port Timing, I2C Mode
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