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參數(shù)資料
| 型號： | CS4340-CZZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 9/25頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 24BIT 96KHZ 101DB 16TSSOP |
| 標準包裝： | 96 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 90mW |
| 工作溫度： | -10°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | 96k |
| 配用： | CDB4340A-ND - EVALUATION BOARD FOR CS4340A |
| 其它名稱： | 598-1049-5 |
CS4340
DS297F3
17
The internal serial clock is utilized when additional de-emphasis control is required. Operation in the Internal
Serial Clock mode is identical to operation with an external SCLK synchronized with LRCK; however, External
SCLK mode is recommended for system clocking applications.
4.2.2 External Serial Clock Mode
The device will enter the External Serial Clock Mode whenever 16 low to high transitions are detected on the
SCLK pin during any phase of the LRCK period. The device will revert to Internal Serial Clock Mode if no low
to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK.
4.3
Digital Interface Format
The device will accept audio samples in several digital interface formats as illustrated in Table 5. The desired format
is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship between LRCK, SCLK and
Input
Digital Interface Format Selection
Internal
MCLK/LRCK
Ratio
I2S up to 24
Bits
Left Justified 24
Bits
Right Justified
24 Bits
Right Justified
16 Bits
SCLK/LRCK
Ratio
512, 256, 128
X-
-
X
32
384, 192
XX
X
48
512, 256, 128
-X
X
-
64
Table 4. Internal SCLK/LRCK Ratio
DIF1
DIF0
DESCRIPTION
FORMAT
FIGURE
00
I2S, up to 24-bit data
01
Left Justified, up to 24-bit data
10
Right Justified, 24-bit Data
11
Right Justified, 16-bit Data
Table 5. Digital Interface Format - DIF1 and DIF0
LR C K
SC L K
Left C ha nnel
R ig h t C ha n nel
SDIN
+3 +2 +1
+5 +4
MSB
-1 -2 -3 -4 -5
+3 +2 +1
+5 +4
-1 -2 -3 -4
LSB
MSB
LSB
Figure 15. CS4340 Format 0 - I2S up to 24-Bit Data
LR C K
SC L K
Left C ha nnel
R ig h t C ha n nel
SDIN
+3 +2 +1
+5 +4
MSB
-1 -2 -3 -4 -5
+3 +2 +1
+5 +4
-1 -2 -3 -4
LSB
MSB
LSB
Figure 16. CS4340 Format 1 - Left Justified up to 24-Bit Data
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| CS4340-CZZR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC 24Bit 96kHz 101dB Stereo DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| CS4340-DS | 制造商:Cirrus Logic 功能描述:DAC 2CH DELTA-SIGMA 24BIT 16SOIC - Rail/Tube |
| CS4340-DSZ | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC 24Bit 96kHz 101dB Stereo DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| CS4340-DSZR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC 24Bit 96kHz 101dB Stereo DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| CS4340-KS | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC 24Bit 96kHz 101dB Stereo DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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