- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1991 > CS4340-CZZ (Cirrus Logic Inc)IC DAC 24BIT 96KHZ 101DB 16TSSOP PDF資料下載
參數(shù)資料
| 型號(hào)： | CS4340-CZZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 24BIT 96KHZ 101DB 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 90mW |
| 工作溫度： | -10°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | 96k |
| 配用： | CDB4340A-ND - EVALUATION BOARD FOR CS4340A |
| 其它名稱： | 598-1049-5 |
CS4340
16
DS297F3
4. APPLICATIONS
4.1
Sample Rate Range/Operational Mode
The device operates in one of two operational modes determined by the Master Clock to Left/Right Clock ratio (see
section 4.2). Sample rates outside the specified range for each mode are not supported.
4.2
System Clocking
The device requires external generation of the master (MCLK) and left/right (LRCK) clocks. The device also requires
external generation of the serial clock (SCLK) if the internal serial clock is not used. The LRCK, defined also as the
input sample rate Fs, must be synchronously derived from MCLK according to specified ratios. The specified ratios
of MCLK to LRCK, along with several standard audio sample rates and the required MCLK frequency, are illustrated
4.2.1 Internal Serial Clock Mode
The device will enter the Internal Serial Clock Mode if no low to high transitions are detected on the SCLK pin
for 2 consecutive periods of LRCK. In this mode, the SCLK is internally derived and synchronous with MCLK
and LRCK. The SCLK/LRCK ratio is either 32, 48, or 64 depending upon the MCLK/LRCK ratio and the Digital
Interface Format selection (see Table 4).
Input Sample Rate (Fs)
MODE
4 kHz - 50 kHz
Single-Speed Mode
50 kHz - 100 kHz
Double-Speed Mode
Table 1. CS4340 Speed Modes
Sample Rate
(kHz)
MCLK (MHz)
256x
384x
512x
32
8.1920
12.2880
16.3840
44.1
11.2896
16.9344
22.5792
48
12.2880
18.4320
24.5760
Table 2. Single-Speed Mode Standard Frequencies
Sample Rate
(kHz)
MCLK (MHz)
128x
192x
64
8.1920
12.2880
88.2
11.2896
16.9344
96
12.2880
18.4320
Table 3. Double-Speed Mode Standard Frequencies
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CS4341-CZZ | IC DAC STER 24BIT 96KHZ 16TSSOP |
| CS4341A-KSZ | IC DAC STER 24BIT 192KHZ 16SOIC |
| CS4351-DZZ | IC DAC STER 112DB 192KHZ 20TSSOP |
| CS4352-DZZ | IC DAC STER 102DB 192KHZ 20TSSOP |
| CS4354-CSZ | IC DAC 24BIT SRL 14SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS4340-CZZR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC 24Bit 96kHz 101dB Stereo DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| CS4340-DS | 制造商:Cirrus Logic 功能描述:DAC 2CH DELTA-SIGMA 24BIT 16SOIC - Rail/Tube |
| CS4340-DSZ | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC 24Bit 96kHz 101dB Stereo DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| CS4340-DSZR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC 24Bit 96kHz 101dB Stereo DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| CS4340-KS | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC 24Bit 96kHz 101dB Stereo DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。