6. Guaranteed by design. See Figure 2. RL and C
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鍨嬭櫉(h脿o)锛� CS4265-CNZ
寤犲晢锛� Cirrus Logic Inc
鏂囦欢闋佹暩(sh霉)锛� 3/46闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC CODEC 24BIT 104DB 32QFN
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 60
椤炲瀷锛� 绔嬮珨鑱查煶闋�
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鍕�(d貌ng)鎱�(t脿i)鑼冨湇锛屾(bi膩o)婧�(zh菙n) ADC / DAC (db)锛� 104 / 104
闆诲 - 闆绘簮锛屾ā鎿細 3.13 V ~ 5.25 V
闆诲 - 闆绘簮锛屾暩(sh霉)瀛楋細 3.13 V ~ 5.25 V
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瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 32-QFN
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 32-QFN 瑁搁湶鐒婄洡锛�5x5锛�
鍖呰锛� 鎵樼洡
鐢�(ch菐n)鍝佺洰閷勯爜闈細 754 (CN2011-ZH PDF)
閰嶇敤锛� 598-1001-ND - BOARD EVAL FOR CS4265 CODEC
鍏跺畠鍚嶇ū锛� 598-1039
DS657F3
11
CS4265
6. Guaranteed by design. See Figure 2. RL and CL reflect the recommended minimum resistance and
maximum capacitance required for the internal op-amp鈥檚 stability. CL affects the dominant pole of the
internal output amp; increasing CL beyond 100 pF can cause the internal op-amp to become unstable.
DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
7. Filter response is guaranteed by design.
8. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs.
9. De-emphasis is available only in Single-Speed Mode.
10. Response is clock dependent and will scale with Fs. Note that the amplitude vs. frequency plots of this
data (Figures 18 to 27) have been normalized to Fs and can be de-normalized by multiplying the X-axis
scale by Fs.
Parameter (Note
Symbol
Min
Typ
Max
Unit
Combined Digital and On-chip Analog Filter Response
Single-Speed Mode
Passband (Note 7)
to -0.1 dB corner
to -3 dB corner
0
-
0.35
0.4992
Fs
Frequency Response 10 Hz to 20 kHz
-0.175
-
+0.01
dB
StopBand
0.5465
-
Fs
StopBand Attenuation
50
-
dB
Group Delay
tgd
-
10/Fs
-
s
De-emphasis Error (Note 9)
Fs = 44.1 kHz
-
+0.05/-0.25
dB
Combined Digital and On-chip Analog Filter Response
Double-Speed Mode
Passband (Note 7)
to -0.1 dB corner
to -3 dB corner
0
-
0.22
0.501
Fs
Frequency Response 10 Hz to 20 kHz
-0.15
-
+0.15
dB
StopBand
0.5770
-
Fs
StopBand Attenuation
55
-
dB
Group Delay
tgd
-
5/Fs
-
s
Combined Digital and On-chip Analog Filter Response
Quad-Speed Mode
Passband (Note 7)
to -0.1 dB corner
to -3 dB corner
0
-
0.110
0.469
Fs
Frequency Response 10 Hz to 20 kHz
-0.12
-
0
dB
StopBand
0.7
-
Fs
StopBand Attenuation
51
-
dB
Group Delay
tgd
-
2.5/Fs
-
s
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
CS4265-CNZ/C1 鍒堕€犲晢:Cirrus Logic 鍔熻兘鎻忚堪:
CS4265-CNZR 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC IC 24bit 192kHz Str Cdc w/PGA &Inpt Mux RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel
CS4265-DNZ 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC Stereo Audio CODEC 104 dB 192 kHz RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel
CS4265-DNZR 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC IC 24-bit 192kHz Str Cdc w/PGA &Inpt Mux RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel
CS4267AM 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:- Bulk
鐧�(f膩)甯冪穵鎬ラ噰璩硷紝3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�

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