Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, C
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� CS4265-CNZ
寤犲晢锛� Cirrus Logic Inc
鏂囦欢闋佹暩(sh霉)锛� 15/46闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC CODEC 24BIT 104DB 32QFN
妯欐簴鍖呰锛� 60
椤炲瀷锛� 绔嬮珨鑱查煶闋�
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� PCM 闊抽牷鎺ュ彛
鍒嗚鲸鐜囷紙浣嶏級锛� 24 b
ADC / DAC 鏁�(sh霉)閲忥細 2 / 2
涓夎绌嶅垎瑾�(di脿o)璁婏細 鏄�
鍕曟厠(t脿i)鑼冨湇锛屾婧� ADC / DAC (db)锛� 104 / 104
闆诲 - 闆绘簮锛屾ā鎿細 3.13 V ~ 5.25 V
闆诲 - 闆绘簮锛屾暩(sh霉)瀛楋細 3.13 V ~ 5.25 V
宸ヤ綔婧害锛� -10°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 32-QFN
渚涙噳鍟嗚ō鍌欏皝瑁濓細 32-QFN 瑁搁湶鐒婄洡锛�5x5锛�
鍖呰锛� 鎵樼洡
鐢�(ch菐n)鍝佺洰閷勯爜闈細 754 (CN2011-ZH PDF)
閰嶇敤锛� 598-1001-ND - BOARD EVAL FOR CS4265 CODEC
鍏跺畠鍚嶇ū锛� 598-1039
22
DS657F3
CS4265
SWITCHING CHARACTERISTICS - IC CONTROL PORT
Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL =30pF.
24. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
25. Guaranteed by design.
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
kHz
RESET Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
s
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
s
Clock Low time
tlow
4.7
-
s
Clock High Time
thigh
4.0
-
s
Setup Time for Repeated Start Condition
tsust
4.7
-
s
SDA Hold Time from SCL Falling
thdd
0-
s
SDA Setup time to SCL Rising
tsud
250
-
ns
Rise Time of SCL and SDA
trc, trd
-1
s
Fall Time SCL and SDA
tfc, tfd
-
300
ns
Setup Time for Stop Condition
tsusp
4.7
-
s
Acknowledge Delay from SCL Falling
tack
300
1000
ns
t buf
t hdst
t
low
t
hdd
t high
t sud
Stop
Start
SDA
SC L
t irs
RS T
t hdst
t rc
t fc
t sust
t susp
Start
Stop
Repeated
t rd
t fd
t ack
Figure 8. Control Port Timing - IC Format
鐩搁棞PDF璩囨枡
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鐩搁棞浠ｇ悊鍟�/鎶€琛撳弮鏁�(sh霉)
鍙冩暩(sh霉)鎻忚堪
CS4265-CNZ/C1 鍒堕€犲晢:Cirrus Logic 鍔熻兘鎻忚堪:
CS4265-CNZR 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC IC 24bit 192kHz Str Cdc w/PGA &Inpt Mux RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel
CS4265-DNZ 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC Stereo Audio CODEC 104 dB 192 kHz RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel
CS4265-DNZR 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC IC 24-bit 192kHz Str Cdc w/PGA &Inpt Mux RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel
CS4267AM 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:- Bulk
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