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參數(shù)資料
| 型號： | CS4202-JQZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 65/66頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC AUDIO '97 48-TQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 音頻編解碼器 '97 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 1 / 1 |
| 三角積分調(diào)變： | 是 |
| 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 90 / 90 |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（9x9） |
| 包裝： | 帶卷 (TR) |
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Micrel, Inc.
MIC3001
August 2004
8
M9999-082404-A
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number
Pin Name
Pin Function
11
TXDISABLE
Digital Input; Active High. The transmitter is disabled when this line is high or the STXDIS bit
is set. The state of this input is always reflected in the TXDIS bit.
12
DATA
Digital I/O; Open-drain. Bi-directional serial data input/output.
13
CLK
Digital Input; Serial bit clock input.
14
VIN
If bit 4 (IE) in USRCTL register is set to 0 (default), this pin is configured as analog input. If
IE bit is set to 1, this pin is configured as open-drain output. Analog Input: Multiplexed A/D
input for monitoring supply voltage. 0V to 5.5V input range. Open-drain output: outputs the
internally generated interrupt signal /INT.
15
RSIN
Digital Input; Rate Select Input; ORed with rate select bit to determine the state of the
RSOUT pin. The state of this pin is always reflected in the RSEL bit.
16
GNDD
Ground return for digital functions.
17
NC
No connection. This pin is used for test purposes and must be left unconnected.
18
VDDD
Power supply input for digital functions.
19
RXLOS
Digital Output; Active-High/Open-Drain. Indicates the loss of the received signal as indicated
by a level of received optical power below the programmed RXLOS comparator threshold;
may be wire-ORed with external signals. Low indicates normal operation. RXLOS is de-
asserted when VRX > LOSFLTn. The LOS bit reflects the state of RXLOS whether driven by
the MIC3001 or an external circuit.
20
RSOUT (GPO)
Digital Output. Open-Drain or push-pull. When used as rate select output, this output is
controlled by the SRSEL bit ORed with RSIN input and is open drain only. When used as a
general-purpose, non-volatile output, it is controlled by the GPO configuration bits in
OEMCFG3.
21
COMP
Analog Output, compensation terminal. Connect a capacitor between this pin and GNDA or
VDDA with appropriate value to tune the APC loop time constant to a desirable value.
22
VBIAS
Analog Output. Buffered DAC output capable of sourcing or sinking up to 10mA under
control of the APC function to drive an external transistor for laser diode D.C. bias. The
output and feedback polarity are programmable to accommodate either a NPN or an PNP
transistor to drive a common-anode or common-cathode laser diode.
23
VMOD–
Analog Input. Inverting terminal of VMOD buffer op-amp. Connect to VMOD+ (gain = 1) or
feedback resistors network to set a different gain
24
VMOD+
Analog Output. Buffered DAC output to set the modulation current on the laser driver IC.
Operates with either a 0– VREF or a (VDD–VREF) – VDD output swing so as to generate
either a ground-referenced or a VDD referenced programmed voltage. A simple external
circuit can be used to generate a programmable current for those drivers that require a
current rather than a voltage input. See “Applications Information” section for more details.
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