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參數(shù)資料
| 型號： | CS4202-JQZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 52/66頁 |
| 文件大小： | 0K |
| 描述： | IC CODEC AUDIO '97 48-TQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 音頻編解碼器 '97 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 1 / 1 |
| 三角積分調(diào)變： | 是 |
| 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 90 / 90 |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（9x9） |
| 包裝： | 帶卷 (TR) |
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Micrel, Inc.
MIC3001
August 2004
56
M9999-082404-A
hbwhelp@micrel.com or (408) 955-1690
Data Ready Flags (DATARDY)
D[7]
TRDY
read/write
D[6]
VRDY
read/write
D[5]
IRDY
read/write
D[4]
TXRDY
read/write
D[3]
RXDY
read/write
D[2]
reserved
D[1]
reserved
D[0]
reserved
Default Value
0000 0000b = 00h
Serial Address
A2h = 1010001b
Byte Address
254 = FEh
When the A/D conversion for a given parameter is completed and the results available to the host, the corresponding data ready
flag will be set. The flag will be cleared when the host reads the corresponding result register.
Bit(s)
Function
Operation
D[7]
TRDY
Temperature data ready flag
0 = old data; 1 = new data ready
D[6]
VRDY
Voltage data ready flag
0 = old data; 1 = new data ready
D[5]
IRDY
Bias current data ready flag
0 = old data; 1 = new data ready
D[4]
TXRDY
Transmit power data ready flag
0 = old data; 1 = new data ready
D[3]
RXRDY
Receive power data ready flag
0 = old data; 1 = new data ready
D[2:0]
Reserved
USER Control Register (USRCTL)
D[7]
read/write
D[6]
PORM
read/write
D[5]
PORS
read/write
D[4]
IE
read/write
D[3]
APCSEL
read/write
D[2]
read/write
D[1]
read/write
D[0]
read/write
Default Value
0010 0000b = 20h
Serial Address
A2h = 1010001b
Byte Address
255 = FFh
This register provides for control of the nominal APC setpoint and management of interrupts by the end-user. APCSEL[1:0]
select which of the APC setpoint registers, APCSET0, APCSET1, or APCSET2 are used as the nominal automatic power
control setpoint.
IE must be set for any interrupts to occur. If PORM is set, the power-on event will generate an interrupt and warm resets using
RST will not generate a POR interrupt. When a power-on interrupt occurs, assuming PORM=1, PORS will be set. PORS will be
cleared and the interrupt output de-asserted when USRCTL is read by the host. If IE is set while /INT is asserted, /INT will be
de-asserted. The host must still clear the various status flags by reading them. If PORM is set following the setting of PORS,
PORS will remain set, and /INT will not be de-asserted, until USRCTL is read by the host.
PORM, IE, and APCSEL are non-volatile and will be maintained through power and reset cycles. A valid USER password is
required for access to this register.
Bit
Function
Operation
D[7]
Reserved
Always write as zero; reads undefined.
D[6]
PORM
Power-on interrupt mask
1 = POR interrupts enabled; 0 = disabled; read/write;
non-volatile.
D[5]
PORS
Power-on interrupt flag
1 = POR interrupt occurred; 0 = no POR interrupt;
read-only.
D[4]
IE
Global interrupt enable
1 = enabled; 0 = disabled; read/write; non-volatile.
D[3]
APCSEL
Selects APC setpoint register
00 = APCSET0, 01 = APCSET1, 10 = APCSET2;
11 = reserved; read/write; non-volatile.
D[2:0]
Reserved
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