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參數資料
| 型號： | CS2300P-DZZR |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | PLL合成/DDS/VCOs |
| 中文描述： | PHASE LOCKED LOOP, 30 MHz, PDSO10 |
| 封裝： | 3 MM, LEAD FREE, MO-187, MSOP-10 |
| 文件頁數： | 24/26頁 |
| 文件大?。?/td> | 434K |
| 代理商： | CS2300P-DZZR |
CS2300-OTP
DS844F2
7
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade);
TA = -40°C to +85°C (Automotive Grade); CL =15pF.
Notes:
5. fCLK_OUT = 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] =11.
6. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd
order 100 Hz to 40 kHz bandpass filter.
7. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd
order 100 Hz Highpass filter.
8. 1 UI (unit interval) corresponds to tCLK_IN or 1/fCLK_IN.
Parameters
Symbol
Conditions
Min
Typ
Max
Units
Clock Input Frequency
fCLK_IN
50 Hz
-
30
MHz
Clock Input Pulse Width
pwCLK_IN
fCLK_IN < 175 kHz
fCLK_IN > 175 kHz
140
10
-
ns
PLL Clock Output Frequency
fCLK_OUT
6-
75
MHz
PLL Clock Output Duty Cycle
tOD
Measured at VD/2
45
50
55
%
Clock Output Rise Time
tOR
20% to 80% of VD
-
1.7
3.0
ns
Clock Output Fall Time
tOF
80% to 20% of VD
-
1.7
3.0
ns
Period Jitter
tJIT
-
35
-
ps rms
Base Band Jitter (100 Hz to 40 kHz)
(Notes 5, 6)
-
50
-
ps rms
Wide Band JItter (100 Hz Corner)
(Notes 5, 7)
-
150
-
ps rms
PLL Lock Time - CLK_IN (Note 8)tLC
fCLK_IN < 200 kHz
fCLK_IN > 200 kHz
-
100
1
200
3
UI
ms
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相關代理商/技術參數 |
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| CS2300P-EZZ | 功能描述:IC - GENERAL PURPOSE PLL CRYSTAL 制造商:cirrus logic inc. 系列:* 零件狀態(tài):在售 標準包裝:96 |
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