- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗10253 > CS181022-CQZ (Cirrus Logic Inc)IC COBRANET CS181022 144LQFP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | CS181022-CQZ |
| 寤犲晢锛� | Cirrus Logic Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 5/15闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC COBRANET CS181022 144LQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 60 |
| 绯诲垪锛� | CobraNet® |
| 椤炲瀷锛� | 闊抽牷铏曠悊鍣� |
| 鎳�(y墨ng)鐢細 | 缍�(w菐ng)绲�(lu貌) |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 144-LQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 144-LQFP锛�20x20锛� |
| 鍖呰锛� | 鎵樼洡 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 758 (CN2011-ZH PDF) |
| 閰嶇敤锛� | 598-1021-ND - MODULE COBRANET 4961 CM2 FB 598-1020-ND - MODULE COBRANET 1810 CM2 MT |
| 鍏跺畠鍚嶇ū锛� | 598-1026 |
CobraNet Hardware User鈥檚 Manual
Pinout and Signal Descriptions
DS651UM23
Copyright 2005 Cirrus Logic, Inc.
13
Version 2.3
4.2.3 Synchronous Serial (Audio) Signals
The synchronous serial interfaces are used to bring digital audio into and out of the
system. Typically the synchronous serial is wired to ADCs and/or DACs. Detailed timing
and format is described in "Digital Audio Interface" on page 19.
4.2.4 Audio Clock Signals
See "Synchronization" on page 17 for an overview of synchronization modes and issues.
*An external multiplexor controlled by this pin is required for full MCLK_IN and MCLK out
implementation.
Signal
Description
Direction
CM-2
Pin #
CS1810xx/
CS4961xx Pin #
Notes
DAO1_SCLK
Audio Bit Clock
Out
J3:A7
20
Synchronous serial bit clock.
64 FS for CS18100x & CS49610x (2x1 channel)
64 FS for CS18101x & CS49611x (2x4
channels)
128 FS for CS18102x & CS49612x (4x4
channels)
Typically tied to DAI1_SCLK.
DAO1_DATA[3:0]
Audio Output
Data
Out
J3:A18,
B18
15-17, 19
Output synchronous serial audio data
DAO1_DATA[3:1] not used for CS18100x &
CS49610x.
DAI1_DATA[3:0]
Audio Input Data
In
J3:
A[15:12]
131, 132, 134, 135
Input synchronous serial audio data
DAI1_DATA[3:1] not used for CS18100x &
CS49610x.
DAI1_SCLK
Audio Bit Clock
In
J4:A7
137
Should be tied to DAO1_SCLK.
Synchronous serial bit clock.
Signal
Description
Direction
CM-2
Pin #
CS1810xx/
CS4961xx Pin #
Notes
DAI1_LRCLK
Sample clock
input
In
138
Should be tied to DAO1_LRCLK for all devices.
DAO1_LRCLK
(FS1)
Sample clock
output
Out
J3:A3
22
FS1 (word clock) for CS18100x/CS49610x and
CS18101x/CS49611x.
DAO2_LRCLK
(FS1)
Sample clock
output
Out
J3:A3
14
FS1 (word clock) for CS18102x & CS49612x.
REFCLK_IN
Reference clock
In
J3:A6
97
Clock input for synchronizing network to an
external clock source, for redundancy control
and synchronization of FS divider chain to
external source. See "Synchronization" on
page 17 for more detail.
MCLK_IN
Master audio
clock input
In
J3:A5
8*
For systems featuring multiple CobraNet
interfaces operating off a common master
clock. See "Synchronization" on page 17 for
more detail.
MCLK_OUT
Master audio
clock output
Out
J3:A4
8*
Low jitter 24.576 MHz master audio clock.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| AD1896AYRSZ | IC CONV SAMPLE RATE ASYNC 28SSOP |
| CS6422-CSZ | IC SPEAKERPHONE ENHANCED 20SOIC |
| CXC3106A14S7P | CONN PLUG 3POS STRGHT PIN |
| CS8421-CZZ | IC SAMPLE RATE CONVERTER 20TSSOP |
| CS8406-CZZ | IC XMITTER DGTL 192KHZ 28TSSOP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| CS181022-CQZ/A1 | 鍒堕€犲晢:CIRRUS 鍒堕€犲晢鍏ㄧū:Cirrus Logic 鍔熻兘鎻忚堪:Digital Audio Networking Processor |
| CS181022-CQZR | 鍔熻兘鎻忚堪:闊抽牷 DSP IC CobraNet Audio Networking Processor RoHS:鍚� 鍒堕€犲晢:Texas Instruments 宸ヤ綔闆绘簮闆诲: 闆绘簮闆绘祦: 宸ヤ綔婧害鑼冨湇: 瀹夎棰�(f膿ng)鏍�: 灏佽 / 绠遍珨: 灏佽:Tube |
| CS1810XX | 鍒堕€犲晢:CIRRUS 鍒堕€犲晢鍏ㄧū:Cirrus Logic 鍔熻兘鎻忚堪:New CobraNet Silicon Series Ideal for Digital Audio Networking Applications |
| CS1812-04 | 鍒堕€犲晢:CITRUSCOM 鍔熻兘鎻忚堪:EMI with ESD protection IC uDFN-8L |
| CS1812-08 | 鍒堕€犲晢:CITRUSCOM 鍔熻兘鎻忚堪: |
鐧�(f膩)甯冪穵鎬ラ噰璩�锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�
